From 51dc4b05494e5b6ddf32ce38cca70b1af54b091d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Thu, 17 Oct 2024 01:50:36 +0200 Subject: [PATCH] std.Target: Use ppc64 as the generic CPU model for powerpc64le. ppc64le remains the baseline CPU model. Note that there's nothing about little endian, 64-bit PowerPC that requires the features in the ppc64le model; the reason it exists is that 64-bit PowerPC wasn't really used in little endian mode prior to those features being commonplace. That makes the ppc64le model a good baseline model, but not the right choice for a generic model. --- lib/std/Target.zig | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index c1714629bf..d73612e77b 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1811,10 +1811,8 @@ pub const Cpu = struct { .mips, .mipsel => &mips.cpu.mips32, .mips64, .mips64el => &mips.cpu.mips64, .msp430 => &msp430.cpu.generic, - .powerpc => &powerpc.cpu.ppc, - .powerpcle => &powerpc.cpu.ppc, - .powerpc64 => &powerpc.cpu.ppc64, - .powerpc64le => &powerpc.cpu.ppc64le, + .powerpc, .powerpcle => &powerpc.cpu.ppc, + .powerpc64, .powerpc64le => &powerpc.cpu.ppc64, .propeller1 => &propeller.cpu.generic, .propeller2 => &propeller.cpu.generic, .amdgcn => &amdgpu.cpu.generic, @@ -1861,6 +1859,7 @@ pub const Cpu = struct { .hexagon => &hexagon.cpu.hexagonv60, // gcc/clang do not have a generic hexagon model. .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model. .loongarch64 => &loongarch.cpu.loongarch64, + .powerpc64le => &powerpc.cpu.ppc64le, .riscv32 => &riscv.cpu.baseline_rv32, .riscv64 => &riscv.cpu.baseline_rv64, .nvptx, .nvptx64 => &nvptx.cpu.sm_20,