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aarch64: fix behavior failures

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This commit is contained in:
Jacob Young 2025-09-12 00:30:20 -04:00 committed by Andrew Kelley
parent 60cdacaff2
commit 5144f10ec9
3 changed files with 28 additions and 31 deletions
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56
src/codegen/aarch64/Select.zig
View File

@ -5821,29 +5821,21 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory,
if (air.next()) |next_air_tag| continue :air_tag next_air_tag; if (air.next()) |next_air_tag| continue :air_tag next_air_tag;
}, },
.unwrap_errunion_err_ptr => { .unwrap_errunion_err_ptr => {
if (isel.live_values.fetchRemove(air.inst_index)) |error_ptr_vi| unused: { if (isel.live_values.fetchRemove(air.inst_index)) |error_vi| {
defer error_ptr_vi.value.deref(isel); defer error_vi.value.deref(isel);
const ty_op = air.data(air.inst_index).ty_op; const ty_op = air.data(air.inst_index).ty_op;
switch (codegen.errUnionErrorOffset( const error_union_ptr_ty = isel.air.typeOf(ty_op.operand, ip);
isel.air.typeOf(ty_op.operand, ip).childType(zcu).errorUnionPayload(zcu), const error_union_ptr_info = error_union_ptr_ty.ptrInfo(zcu);
zcu, const error_union_ptr_vi = try isel.use(ty_op.operand);
)) { const error_union_ptr_mat = try error_union_ptr_vi.matReg(isel);
0 => try error_ptr_vi.value.move(isel, ty_op.operand), _ = try error_vi.value.load(isel, ty_op.ty.toType(), error_union_ptr_mat.ra, .{
else => |error_offset| { .offset = codegen.errUnionErrorOffset(
const error_ptr_ra = try error_ptr_vi.value.defReg(isel) orelse break :unused; ZigType.fromInterned(error_union_ptr_info.child).errorUnionPayload(zcu),
const error_union_ptr_vi = try isel.use(ty_op.operand); zcu,
const error_union_ptr_mat = try error_union_ptr_vi.matReg(isel); ),
const lo12: u12 = @truncate(error_offset >> 0); .@"volatile" = error_union_ptr_info.flags.is_volatile,
const hi12: u12 = @intCast(error_offset >> 12); });
if (hi12 > 0) try isel.emit(.add( try error_union_ptr_mat.finish(isel);
error_ptr_ra.x(),
if (lo12 > 0) error_ptr_ra.x() else error_union_ptr_mat.ra.x(),
.{ .shifted_immediate = .{ .immediate = hi12, .lsl = .@"12" } },
));
if (lo12 > 0) try isel.emit(.add(error_ptr_ra.x(), error_union_ptr_mat.ra.x(), .{ .immediate = lo12 }));
try error_union_ptr_mat.finish(isel);
},
}
} }
if (air.next()) |next_air_tag| continue :air_tag next_air_tag; if (air.next()) |next_air_tag| continue :air_tag next_air_tag;
}, },
@ -8031,6 +8023,7 @@ pub fn layout(
while (save_index < saves.len) { while (save_index < saves.len) {
if (save_index + 2 <= saves.len and saves[save_index + 1].needs_restore and if (save_index + 2 <= saves.len and saves[save_index + 1].needs_restore and
saves[save_index + 0].class == saves[save_index + 1].class and saves[save_index + 0].class == saves[save_index + 1].class and
saves[save_index + 0].size == saves[save_index + 1].size and
saves[save_index + 0].offset + saves[save_index + 0].size == saves[save_index + 1].offset) saves[save_index + 0].offset + saves[save_index + 0].size == saves[save_index + 1].offset)
{ {
try isel.emit(.ldp( try isel.emit(.ldp(
@ -8337,7 +8330,7 @@ fn elemPtr(
}), }),
2 => { 2 => {
const shift: u6 = @intCast(@ctz(elem_size)); const shift: u6 = @intCast(@ctz(elem_size));
const temp_ra = temp_ra: switch (op) { const temp_ra, const free_temp_ra = temp_ra: switch (op) {
.add => switch (base_ra) { .add => switch (base_ra) {
else => { else => {
const temp_ra = try isel.allocIntReg(); const temp_ra = try isel.allocIntReg();
@ -8346,7 +8339,7 @@ fn elemPtr(
.register = temp_ra.x(), .register = temp_ra.x(),
.shift = .{ .lsl = shift }, .shift = .{ .lsl = shift },
} })); } }));
break :temp_ra temp_ra; break :temp_ra .{ temp_ra, true };
}, },
.zr => { .zr => {
if (shift > 0) try isel.emit(.ubfm(elem_ptr_ra.x(), elem_ptr_ra.x(), .{ if (shift > 0) try isel.emit(.ubfm(elem_ptr_ra.x(), elem_ptr_ra.x(), .{
@ -8354,7 +8347,7 @@ fn elemPtr(
.immr = -%shift, .immr = -%shift,
.imms = ~shift, .imms = ~shift,
})); }));
break :temp_ra elem_ptr_ra; break :temp_ra .{ elem_ptr_ra, false };
}, },
}, },
.sub => { .sub => {
@ -8364,10 +8357,10 @@ fn elemPtr(
.register = temp_ra.x(), .register = temp_ra.x(),
.shift = .{ .lsl = shift }, .shift = .{ .lsl = shift },
} })); } }));
break :temp_ra temp_ra; break :temp_ra .{ temp_ra, true };
}, },
}; };
defer if (temp_ra != elem_ptr_ra) isel.freeReg(temp_ra); defer if (free_temp_ra) isel.freeReg(temp_ra);
try isel.emit(.add(temp_ra.x(), index_mat.ra.x(), .{ .shifted_register = .{ try isel.emit(.add(temp_ra.x(), index_mat.ra.x(), .{ .shifted_register = .{
.register = index_mat.ra.x(), .register = index_mat.ra.x(),
.shift = .{ .lsl = @intCast(63 - @clz(elem_size) - shift) }, .shift = .{ .lsl = @intCast(63 - @clz(elem_size) - shift) },
@ -9296,7 +9289,14 @@ pub const Value = struct {
part_offset -= part_size; part_offset -= part_size;
var wrapped_res_part_it = res_vi.field(ty, part_offset, part_size); var wrapped_res_part_it = res_vi.field(ty, part_offset, part_size);
const wrapped_res_part_vi = try wrapped_res_part_it.only(isel); const wrapped_res_part_vi = try wrapped_res_part_it.only(isel);
const wrapped_res_part_ra = try wrapped_res_part_vi.?.defReg(isel) orelse if (need_carry) .zr else continue; const wrapped_res_part_ra = wrapped_res_part_ra: {
const overflow_ra_lock: RegLock = switch (opts.overflow) {
.ra => |ra| isel.lockReg(ra),
else => .empty,
};
defer overflow_ra_lock.unlock(isel);
break :wrapped_res_part_ra try wrapped_res_part_vi.?.defReg(isel) orelse if (need_carry) .zr else continue;
};
const unwrapped_res_part_ra = unwrapped_res_part_ra: { const unwrapped_res_part_ra = unwrapped_res_part_ra: {
if (!need_wrap) break :unwrapped_res_part_ra wrapped_res_part_ra; if (!need_wrap) break :unwrapped_res_part_ra wrapped_res_part_ra;
if (int_info.bits % 32 == 0) { if (int_info.bits % 32 == 0) {

1
test/behavior/switch_on_captured_error.zig
View File

@ -300,7 +300,6 @@ test "switch on error union catch capture" {
} }
test "switch on error union if else capture" { test "switch on error union if else capture" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest; if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest; if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;

2
test/behavior/try.zig
View File

@ -122,7 +122,6 @@ test "'return try' through conditional" {
} }
test "try ptr propagation const" { test "try ptr propagation const" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest; if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
@ -155,7 +154,6 @@ test "try ptr propagation const" {
} }
test "try ptr propagation mutate" { test "try ptr propagation mutate" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest; if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;