mirror of
https://github.com/ziglang/zig.git
synced 2026-02-14 05:20:34 +00:00
update most target CPU features to llvm12
The tools/update_cpu_features script is coming along, and generates correct information for all these targets. The remaining targets are: * arm * aarch64 * amdgpu * riscv I will commit them once the issues with the updater tool are resolved.
This commit is contained in:
Andrew Kelley
parent
59b4facd34
commit
50a5fc98dc
@ -1070,17 +1070,13 @@ pub const Target = struct {
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}
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}
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/// Returns a name that matches the lib/std/target/* directory name.
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/// Returns a name that matches the lib/std/target/* source file name.
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pub fn genericName(arch: Arch) []const u8 {
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return switch (arch) {
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.arm, .armeb, .thumb, .thumbeb => "arm",
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.aarch64, .aarch64_be, .aarch64_32 => "aarch64",
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.avr => "avr",
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.bpfel, .bpfeb => "bpf",
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.csky => "csky",
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.hexagon => "hexagon",
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.mips, .mipsel, .mips64, .mips64el => "mips",
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.msp430 => "msp430",
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.powerpc, .powerpc64, .powerpc64le => "powerpc",
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.amdgcn => "amdgpu",
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.riscv32, .riscv64 => "riscv",
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@ -1111,6 +1107,7 @@ pub const Target = struct {
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.s390x => &systemz.all_features,
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.i386, .x86_64 => &x86.all_features,
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.nvptx, .nvptx64 => &nvptx.all_features,
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.ve => &ve.all_features,
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.wasm32, .wasm64 => &wasm.all_features,
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else => &[0]Cpu.Feature{},
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@ -1134,6 +1131,7 @@ pub const Target = struct {
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.s390x => comptime allCpusFromDecls(systemz.cpu),
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.i386, .x86_64 => comptime allCpusFromDecls(x86.cpu),
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.nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu),
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.ve => comptime allCpusFromDecls(ve.cpu),
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.wasm32, .wasm64 => comptime allCpusFromDecls(wasm.cpu),
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else => &[0]*const Model{},
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@ -1188,12 +1186,13 @@ pub const Target = struct {
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.amdgcn => &amdgpu.cpu.generic,
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.riscv32 => &riscv.cpu.generic_rv32,
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.riscv64 => &riscv.cpu.generic_rv64,
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.sparc, .sparcel => &sparc.cpu.v8,
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.sparc, .sparcel => &sparc.cpu.generic,
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.sparcv9 => &sparc.cpu.v9,
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.s390x => &systemz.cpu.generic,
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.i386 => &x86.cpu._i386,
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.x86_64 => &x86.cpu.x86_64,
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.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
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.ve => &ve.cpu.generic,
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.wasm32, .wasm64 => &wasm.cpu.generic,
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else => &S.generic_model,
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@ -1207,6 +1206,7 @@ pub const Target = struct {
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.riscv64 => &riscv.cpu.baseline_rv64,
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.i386 => &x86.cpu.pentium4,
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.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
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.sparc, .sparcel => &sparc.cpu.v8,
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else => generic(arch),
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};
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@ -1,8 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2021 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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@ -163,7 +160,6 @@ pub const all_features = blk: {
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.dependencies = featureSet(&[_]Feature{
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.avr0,
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.@"break",
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.memmappedregs,
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.sram,
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.tinyencoding,
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}),
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@ -1859,7 +1855,7 @@ pub const cpu = struct {
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.name = "atxmega16e5",
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.llvm_name = "atxmega16e5",
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.features = featureSet(&[_]Feature{
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.xmega,
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.xmegau,
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}),
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};
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pub const atxmega192a3 = CpuModel{
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@ -1,8 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2021 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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@ -1,8 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2021 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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@ -92,7 +89,6 @@ pub const all_features = blk: {
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.llvm_name = "hvxv62",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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.hvxv60,
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}),
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};
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@ -100,8 +96,6 @@ pub const all_features = blk: {
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.llvm_name = "hvxv65",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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.hvxv60,
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.hvxv62,
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}),
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};
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@ -109,9 +103,6 @@ pub const all_features = blk: {
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.llvm_name = "hvxv66",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvx,
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.hvxv60,
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.hvxv62,
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.hvxv65,
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.zreg,
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}),
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@ -120,9 +111,6 @@ pub const all_features = blk: {
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.llvm_name = "hvxv67",
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.description = "Hexagon HVX instructions",
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.dependencies = featureSet(&[_]Feature{
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.hvxv60,
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.hvxv62,
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.hvxv65,
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.hvxv66,
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}),
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};
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@ -248,7 +236,6 @@ pub const cpu = struct {
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.memops,
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.nvj,
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.nvs,
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.packets,
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.prev65,
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.small_data,
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.v5,
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@ -265,7 +252,6 @@ pub const cpu = struct {
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.memops,
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.nvj,
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.nvs,
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.packets,
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.prev65,
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.small_data,
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.v5,
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@ -280,7 +266,6 @@ pub const cpu = struct {
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.memops,
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.nvj,
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.nvs,
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.packets,
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.prev65,
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.small_data,
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.v5,
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@ -296,7 +281,6 @@ pub const cpu = struct {
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.memops,
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.nvj,
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.nvs,
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.packets,
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.prev65,
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.small_data,
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.v5,
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@ -313,7 +297,6 @@ pub const cpu = struct {
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.memops,
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.nvj,
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.nvs,
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.packets,
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.prev65,
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.small_data,
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.v5,
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@ -332,7 +315,6 @@ pub const cpu = struct {
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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@ -351,7 +333,6 @@ pub const cpu = struct {
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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@ -371,7 +352,6 @@ pub const cpu = struct {
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.memops,
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.nvj,
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.nvs,
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.packets,
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.small_data,
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.v5,
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.v55,
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@ -391,7 +371,6 @@ pub const cpu = struct {
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.mem_noshuf,
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.memops,
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.nvs,
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.packets,
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.small_data,
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.tinycore,
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.v5,
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@ -1,8 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2021 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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@ -108,7 +105,6 @@ pub const all_features = blk: {
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.llvm_name = "dspr3",
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.description = "Mips DSP-R3 ASE",
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.dependencies = featureSet(&[_]Feature{
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.dsp,
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.dspr2,
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}),
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};
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@ -301,10 +297,8 @@ pub const all_features = blk: {
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.llvm_name = "mips64r6",
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.description = "Mips64r6 ISA Support [experimental]",
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.dependencies = featureSet(&[_]Feature{
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.abs2008,
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.mips32r6,
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.mips64r5,
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.nan2008,
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}),
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};
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result[@enumToInt(Feature.msa)] = .{
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@ -515,16 +509,13 @@ pub const cpu = struct {
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.llvm_name = "octeon",
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.features = featureSet(&[_]Feature{
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.cnmips,
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.mips64r2,
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}),
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};
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pub const @"octeon+" = CpuModel{
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.name = "octeon+",
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.llvm_name = "octeon+",
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.features = featureSet(&[_]Feature{
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.cnmips,
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.cnmipsp,
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.mips64r2,
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}),
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};
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pub const p5600 = CpuModel{
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@ -1,8 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2021 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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@ -1,8 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2021 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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@ -1,8 +1,5 @@
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// SPDX-License-Identifier: MIT
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// Copyright (c) 2015-2021 Zig Contributors
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// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
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// The MIT license requires this copyright notice to be included in all copies
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// and substantial portions of the software.
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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@ -10,6 +7,7 @@ const CpuModel = std.Target.Cpu.Model;
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pub const Feature = enum {
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@"64bit",
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@"64bitregs",
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aix,
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allow_unaligned_fp_access,
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altivec,
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booke,
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@ -19,6 +17,7 @@ pub const Feature = enum {
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crypto,
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direct_move,
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e500,
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efpu2,
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extdiv,
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fcpsgn,
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float128,
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@ -46,6 +45,7 @@ pub const Feature = enum {
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longcall,
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mfocrf,
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mma,
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modern_aix_as,
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msync,
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paired_vector_memops,
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partword_atomics,
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@ -62,7 +62,6 @@ pub const Feature = enum {
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ppc6xx,
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predictable_select_expensive,
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prefix_instrs,
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qpx,
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recipprec,
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secure_plt,
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slow_popcntd,
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@ -89,6 +88,11 @@ pub const all_features = blk: {
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.description = "Enable 64-bit registers usage for ppc32 [beta]",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.aix)] = .{
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.llvm_name = "aix",
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.description = "AIX OS",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.allow_unaligned_fp_access)] = .{
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.llvm_name = "allow-unaligned-fp-access",
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.description = "CPU does not trap on unaligned FP access",
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@ -142,6 +146,13 @@ pub const all_features = blk: {
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.description = "Enable E500/E500mc instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.efpu2)] = .{
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.llvm_name = "efpu2",
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.description = "Enable Embedded Floating-Point APU 2 instructions",
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.dependencies = featureSet(&[_]Feature{
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.spe,
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}),
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};
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result[@enumToInt(Feature.extdiv)] = .{
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.llvm_name = "extdiv",
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.description = "Enable extended divide instructions",
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@ -311,6 +322,11 @@ pub const all_features = blk: {
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.power9_altivec,
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}),
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};
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result[@enumToInt(Feature.modern_aix_as)] = .{
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.llvm_name = "modern-aix-as",
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.description = "AIX system assembler is modern enough to support new mnes",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.msync)] = .{
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.llvm_name = "msync",
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.description = "Has only the msync instruction instead of sync",
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@ -334,7 +350,6 @@ pub const all_features = blk: {
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.llvm_name = "pcrelative-memops",
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.description = "Enable PC relative Memory Ops",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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.prefix_instrs,
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}),
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};
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@ -378,7 +393,6 @@ pub const all_features = blk: {
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.llvm_name = "power9-vector",
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.description = "Enable POWER9 vector instructions",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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.power8_vector,
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.power9_altivec,
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}),
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@ -412,18 +426,10 @@ pub const all_features = blk: {
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.llvm_name = "prefix-instrs",
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.description = "Enable prefixed instructions",
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.dependencies = featureSet(&[_]Feature{
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.isa_v30_instructions,
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.power8_vector,
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.power9_altivec,
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}),
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};
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result[@enumToInt(Feature.qpx)] = .{
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.llvm_name = null,
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.description = "Enable QPX instructions",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@enumToInt(Feature.recipprec)] = .{
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.llvm_name = "recipprec",
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.description = "Assume higher precision reciprocal estimates",
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@ -479,94 +485,90 @@ pub const all_features = blk: {
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};
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pub const cpu = struct {
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pub const @"ppc440" = CpuModel{
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.name = "ppc440",
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pub const @"440" = CpuModel{
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.name = "440",
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.llvm_name = "440",
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.features = featureSet(&[_]Feature{
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.booke,
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.fres,
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.frsqrte,
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.icbt,
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.isel,
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.msync,
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}),
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};
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pub const @"ppc450" = CpuModel{
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.name = "ppc450",
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pub const @"450" = CpuModel{
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.name = "450",
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.llvm_name = "450",
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.features = featureSet(&[_]Feature{
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.booke,
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.fres,
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.frsqrte,
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.icbt,
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.isel,
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.msync,
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}),
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};
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pub const @"ppc601" = CpuModel{
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.name = "ppc601",
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pub const @"601" = CpuModel{
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.name = "601",
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.llvm_name = "601",
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.features = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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pub const @"ppc602" = CpuModel{
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.name = "ppc602",
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pub const @"602" = CpuModel{
|
||||
.name = "602",
|
||||
.llvm_name = "602",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fpu,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc603" = CpuModel{
|
||||
.name = "ppc603",
|
||||
pub const @"603" = CpuModel{
|
||||
.name = "603",
|
||||
.llvm_name = "603",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fres,
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc603e" = CpuModel{
|
||||
.name = "ppc603e",
|
||||
pub const @"603e" = CpuModel{
|
||||
.name = "603e",
|
||||
.llvm_name = "603e",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fres,
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc603ev" = CpuModel{
|
||||
.name = "ppc603ev",
|
||||
pub const @"603ev" = CpuModel{
|
||||
.name = "603ev",
|
||||
.llvm_name = "603ev",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fres,
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc604" = CpuModel{
|
||||
.name = "ppc604",
|
||||
pub const @"604" = CpuModel{
|
||||
.name = "604",
|
||||
.llvm_name = "604",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fres,
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc604e" = CpuModel{
|
||||
.name = "ppc604e",
|
||||
pub const @"604e" = CpuModel{
|
||||
.name = "604e",
|
||||
.llvm_name = "604e",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fres,
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc620" = CpuModel{
|
||||
.name = "ppc620",
|
||||
pub const @"620" = CpuModel{
|
||||
.name = "620",
|
||||
.llvm_name = "620",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fres,
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc7400" = CpuModel{
|
||||
.name = "ppc7400",
|
||||
pub const @"7400" = CpuModel{
|
||||
.name = "7400",
|
||||
.llvm_name = "7400",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.altivec,
|
||||
@ -574,8 +576,8 @@ pub const cpu = struct {
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc7450" = CpuModel{
|
||||
.name = "ppc7450",
|
||||
pub const @"7450" = CpuModel{
|
||||
.name = "7450",
|
||||
.llvm_name = "7450",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.altivec,
|
||||
@ -583,16 +585,16 @@ pub const cpu = struct {
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc750" = CpuModel{
|
||||
.name = "ppc750",
|
||||
pub const @"750" = CpuModel{
|
||||
.name = "750",
|
||||
.llvm_name = "750",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fres,
|
||||
.frsqrte,
|
||||
}),
|
||||
};
|
||||
pub const @"ppc970" = CpuModel{
|
||||
.name = "ppc970",
|
||||
pub const @"970" = CpuModel{
|
||||
.name = "970",
|
||||
.llvm_name = "970",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
@ -619,7 +621,6 @@ pub const cpu = struct {
|
||||
.frsqrte,
|
||||
.frsqrtes,
|
||||
.fsqrt,
|
||||
.icbt,
|
||||
.isel,
|
||||
.ldbrx,
|
||||
.lfiwax,
|
||||
@ -629,38 +630,10 @@ pub const cpu = struct {
|
||||
.stfiwx,
|
||||
}),
|
||||
};
|
||||
pub const a2q = CpuModel{
|
||||
.name = "a2q",
|
||||
.llvm_name = "a2q",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.booke,
|
||||
.cmpb,
|
||||
.fcpsgn,
|
||||
.fpcvt,
|
||||
.fprnd,
|
||||
.fre,
|
||||
.fres,
|
||||
.frsqrte,
|
||||
.frsqrtes,
|
||||
.fsqrt,
|
||||
.icbt,
|
||||
.isel,
|
||||
.ldbrx,
|
||||
.lfiwax,
|
||||
.mfocrf,
|
||||
.qpx,
|
||||
.recipprec,
|
||||
.slow_popcntd,
|
||||
.stfiwx,
|
||||
}),
|
||||
};
|
||||
pub const e500 = CpuModel{
|
||||
.name = "e500",
|
||||
.llvm_name = "e500",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.booke,
|
||||
.icbt,
|
||||
.isel,
|
||||
.msync,
|
||||
.spe,
|
||||
@ -671,7 +644,6 @@ pub const cpu = struct {
|
||||
.llvm_name = "e500mc",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.booke,
|
||||
.icbt,
|
||||
.isel,
|
||||
.stfiwx,
|
||||
}),
|
||||
@ -682,7 +654,6 @@ pub const cpu = struct {
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.booke,
|
||||
.icbt,
|
||||
.isel,
|
||||
.mfocrf,
|
||||
.stfiwx,
|
||||
@ -694,7 +665,6 @@ pub const cpu = struct {
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.allow_unaligned_fp_access,
|
||||
.altivec,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crypto,
|
||||
@ -711,30 +681,21 @@ pub const cpu = struct {
|
||||
.fuse_store,
|
||||
.htm,
|
||||
.icbt,
|
||||
.isa_v30_instructions,
|
||||
.isa_v31_instructions,
|
||||
.isel,
|
||||
.ldbrx,
|
||||
.lfiwax,
|
||||
.mfocrf,
|
||||
.mma,
|
||||
.paired_vector_memops,
|
||||
.partword_atomics,
|
||||
.pcrelative_memops,
|
||||
.popcntd,
|
||||
.power10_vector,
|
||||
.power8_altivec,
|
||||
.power8_vector,
|
||||
.power9_altivec,
|
||||
.power9_vector,
|
||||
.ppc_postra_sched,
|
||||
.ppc_prera_sched,
|
||||
.predictable_select_expensive,
|
||||
.prefix_instrs,
|
||||
.recipprec,
|
||||
.stfiwx,
|
||||
.two_const_nr,
|
||||
.vsx,
|
||||
}),
|
||||
};
|
||||
pub const g3 = CpuModel{
|
||||
@ -792,7 +753,7 @@ pub const cpu = struct {
|
||||
};
|
||||
pub const ppc32 = CpuModel{
|
||||
.name = "ppc32",
|
||||
.llvm_name = "ppc",
|
||||
.llvm_name = "ppc32",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.hard_float,
|
||||
}),
|
||||
@ -816,7 +777,6 @@ pub const cpu = struct {
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.allow_unaligned_fp_access,
|
||||
.altivec,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crypto,
|
||||
@ -840,13 +800,11 @@ pub const cpu = struct {
|
||||
.mfocrf,
|
||||
.partword_atomics,
|
||||
.popcntd,
|
||||
.power8_altivec,
|
||||
.power8_vector,
|
||||
.predictable_select_expensive,
|
||||
.recipprec,
|
||||
.stfiwx,
|
||||
.two_const_nr,
|
||||
.vsx,
|
||||
}),
|
||||
};
|
||||
pub const pwr10 = CpuModel{
|
||||
@ -855,7 +813,6 @@ pub const cpu = struct {
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.allow_unaligned_fp_access,
|
||||
.altivec,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crypto,
|
||||
@ -872,30 +829,21 @@ pub const cpu = struct {
|
||||
.fuse_store,
|
||||
.htm,
|
||||
.icbt,
|
||||
.isa_v30_instructions,
|
||||
.isa_v31_instructions,
|
||||
.isel,
|
||||
.ldbrx,
|
||||
.lfiwax,
|
||||
.mfocrf,
|
||||
.mma,
|
||||
.paired_vector_memops,
|
||||
.partword_atomics,
|
||||
.pcrelative_memops,
|
||||
.popcntd,
|
||||
.power10_vector,
|
||||
.power8_altivec,
|
||||
.power8_vector,
|
||||
.power9_altivec,
|
||||
.power9_vector,
|
||||
.ppc_postra_sched,
|
||||
.ppc_prera_sched,
|
||||
.predictable_select_expensive,
|
||||
.prefix_instrs,
|
||||
.recipprec,
|
||||
.stfiwx,
|
||||
.two_const_nr,
|
||||
.vsx,
|
||||
}),
|
||||
};
|
||||
pub const pwr3 = CpuModel{
|
||||
@ -1000,7 +948,6 @@ pub const cpu = struct {
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.allow_unaligned_fp_access,
|
||||
.altivec,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.extdiv,
|
||||
@ -1029,7 +976,6 @@ pub const cpu = struct {
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.allow_unaligned_fp_access,
|
||||
.altivec,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crypto,
|
||||
@ -1053,13 +999,11 @@ pub const cpu = struct {
|
||||
.mfocrf,
|
||||
.partword_atomics,
|
||||
.popcntd,
|
||||
.power8_altivec,
|
||||
.power8_vector,
|
||||
.predictable_select_expensive,
|
||||
.recipprec,
|
||||
.stfiwx,
|
||||
.two_const_nr,
|
||||
.vsx,
|
||||
}),
|
||||
};
|
||||
pub const pwr9 = CpuModel{
|
||||
@ -1068,7 +1012,6 @@ pub const cpu = struct {
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.allow_unaligned_fp_access,
|
||||
.altivec,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crypto,
|
||||
@ -1084,16 +1027,12 @@ pub const cpu = struct {
|
||||
.fsqrt,
|
||||
.htm,
|
||||
.icbt,
|
||||
.isa_v30_instructions,
|
||||
.isel,
|
||||
.ldbrx,
|
||||
.lfiwax,
|
||||
.mfocrf,
|
||||
.partword_atomics,
|
||||
.popcntd,
|
||||
.power8_altivec,
|
||||
.power8_vector,
|
||||
.power9_altivec,
|
||||
.power9_vector,
|
||||
.ppc_postra_sched,
|
||||
.ppc_prera_sched,
|
||||
@ -1102,7 +1041,6 @@ pub const cpu = struct {
|
||||
.stfiwx,
|
||||
.two_const_nr,
|
||||
.vectors_use_two_units,
|
||||
.vsx,
|
||||
}),
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
// Copyright (c) 2015-2021 Zig Contributors
|
||||
// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
|
||||
// The MIT license requires this copyright notice to be included in all copies
|
||||
// and substantial portions of the software.
|
||||
//! This file is auto-generated by tools/update_cpu_features.zig.
|
||||
|
||||
const std = @import("../std.zig");
|
||||
const CpuFeature = std.Target.Cpu.Feature;
|
||||
const CpuModel = std.Target.Cpu.Model;
|
||||
@ -160,6 +157,11 @@ pub const cpu = struct {
|
||||
.llvm_name = "f934",
|
||||
.features = featureSet(&[_]Feature{}),
|
||||
};
|
||||
pub const generic = CpuModel{
|
||||
.name = "generic",
|
||||
.llvm_name = "generic",
|
||||
.features = featureSet(&[_]Feature{}),
|
||||
};
|
||||
pub const gr712rc = CpuModel{
|
||||
.name = "gr712rc",
|
||||
.llvm_name = "gr712rc",
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
// Copyright (c) 2015-2021 Zig Contributors
|
||||
// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
|
||||
// The MIT license requires this copyright notice to be included in all copies
|
||||
// and substantial portions of the software.
|
||||
//! This file is auto-generated by tools/update_cpu_features.zig.
|
||||
|
||||
const std = @import("../std.zig");
|
||||
const CpuFeature = std.Target.Cpu.Feature;
|
||||
const CpuModel = std.Target.Cpu.Model;
|
||||
|
||||
36
lib/std/target/ve.zig
Normal file
36
lib/std/target/ve.zig
Normal file
@ -0,0 +1,36 @@
|
||||
//! This file is auto-generated by tools/update_cpu_features.zig.
|
||||
|
||||
const std = @import("../std.zig");
|
||||
const CpuFeature = std.Target.Cpu.Feature;
|
||||
const CpuModel = std.Target.Cpu.Model;
|
||||
|
||||
pub const Feature = enum {
|
||||
vpu,
|
||||
};
|
||||
|
||||
pub usingnamespace CpuFeature.feature_set_fns(Feature);
|
||||
|
||||
pub const all_features = blk: {
|
||||
const len = @typeInfo(Feature).Enum.fields.len;
|
||||
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
|
||||
var result: [len]CpuFeature = undefined;
|
||||
result[@enumToInt(Feature.vpu)] = .{
|
||||
.llvm_name = "vpu",
|
||||
.description = "Enable the VPU",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
const ti = @typeInfo(Feature);
|
||||
for (result) |*elem, i| {
|
||||
elem.index = i;
|
||||
elem.name = ti.Enum.fields[i].name;
|
||||
}
|
||||
break :blk result;
|
||||
};
|
||||
|
||||
pub const cpu = struct {
|
||||
pub const generic = CpuModel{
|
||||
.name = "generic",
|
||||
.llvm_name = "generic",
|
||||
.features = featureSet(&[_]Feature{}),
|
||||
};
|
||||
};
|
||||
@ -1,8 +1,5 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
// Copyright (c) 2015-2021 Zig Contributors
|
||||
// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
|
||||
// The MIT license requires this copyright notice to be included in all copies
|
||||
// and substantial portions of the software.
|
||||
//! This file is auto-generated by tools/update_cpu_features.zig.
|
||||
|
||||
const std = @import("../std.zig");
|
||||
const CpuFeature = std.Target.Cpu.Feature;
|
||||
const CpuModel = std.Target.Cpu.Model;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user