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stage2 AArch64: implement basic integer rem/mod
This commit is contained in:
joachimschmidt557
parent
8b24c783c5
commit
508b90fcfa
@ -1038,6 +1038,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
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const operand_info = operand_ty.intInfo(self.target.*);
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const dest_ty = self.air.typeOfIndex(inst);
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const dest_abi_size = dest_ty.abiSize(self.target.*);
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const dest_info = dest_ty.intInfo(self.target.*);
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const result: MCValue = result: {
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@ -1047,16 +1048,21 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
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};
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defer if (operand_lock) |lock| self.register_manager.unlockReg(lock);
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const truncated: MCValue = switch (operand_mcv) {
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.register => |r| MCValue{ .register = registerAlias(r, dest_abi_size) },
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else => operand_mcv,
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};
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if (dest_info.bits > operand_info.bits) {
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const dest_mcv = try self.allocRegOrMem(inst, true);
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try self.setRegOrMem(self.air.typeOfIndex(inst), dest_mcv, operand_mcv);
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try self.setRegOrMem(self.air.typeOfIndex(inst), dest_mcv, truncated);
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break :result dest_mcv;
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} else {
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if (self.reuseOperand(inst, operand, 0, operand_mcv)) {
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break :result operand_mcv;
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if (self.reuseOperand(inst, operand, 0, truncated)) {
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break :result truncated;
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} else {
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const dest_mcv = try self.allocRegOrMem(inst, true);
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try self.setRegOrMem(self.air.typeOfIndex(inst), dest_mcv, operand_mcv);
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try self.setRegOrMem(self.air.typeOfIndex(inst), dest_mcv, truncated);
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break :result dest_mcv;
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}
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}
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@ -1145,7 +1151,7 @@ fn trunc(
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return MCValue{ .register = dest_reg };
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} else {
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return self.fail("TODO: truncate to ints > 32 bits", .{});
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return self.fail("TODO: truncate to ints > 64 bits", .{});
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}
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}
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@ -1679,14 +1685,67 @@ fn binOp(
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.Int => {
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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switch (int_info.signedness) {
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.signed => {
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return self.fail("TODO rem/mod on signed integers", .{});
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},
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.unsigned => {
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return self.fail("TODO rem/mod on unsigned integers", .{});
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},
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if (int_info.bits <= 64) {
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if (int_info.signedness == .signed and tag == .mod) {
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return self.fail("TODO mod on signed integers", .{});
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} else {
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const lhs_reg = if (lhs_is_register)
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lhs.register
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else
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try self.register_manager.allocReg(null, gp);
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const rhs_reg = if (rhs_is_register)
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rhs.register
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else
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try self.register_manager.allocReg(null, gp);
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const new_rhs_lock = self.register_manager.lockReg(rhs_reg);
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defer if (new_rhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_regs = try self.register_manager.allocRegs(2, .{ null, null }, gp);
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const dest_regs_locks = self.register_manager.lockRegsAssumeUnused(2, dest_regs);
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defer for (dest_regs_locks) |reg| {
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self.register_manager.unlockReg(reg);
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};
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const quotient_reg = dest_regs[0];
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const remainder_reg = dest_regs[1];
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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_ = try self.addInst(.{
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.tag = switch (int_info.signedness) {
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.signed => .sdiv,
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.unsigned => .udiv,
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},
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.data = .{ .rrr = .{
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.rd = quotient_reg,
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.rn = lhs_reg,
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.rm = rhs_reg,
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} },
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});
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_ = try self.addInst(.{
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.tag = .msub,
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.data = .{ .rrrr = .{
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.rd = remainder_reg,
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.rn = quotient_reg,
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.rm = rhs_reg,
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.ra = lhs_reg,
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} },
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});
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return MCValue{ .register = remainder_reg };
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}
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} else {
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return self.fail("TODO rem/mod for integers with bits > 64", .{});
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@ -190,6 +190,7 @@ pub fn emitMir(
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.movk => try emit.mirMoveWideImmediate(inst),
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.movz => try emit.mirMoveWideImmediate(inst),
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.msub => try emit.mirDataProcessing3Source(inst),
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.mul => try emit.mirDataProcessing3Source(inst),
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.smulh => try emit.mirDataProcessing3Source(inst),
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.smull => try emit.mirDataProcessing3Source(inst),
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@ -1140,14 +1141,31 @@ fn mirMoveWideImmediate(emit: *Emit, inst: Mir.Inst.Index) !void {
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fn mirDataProcessing3Source(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const rrr = emit.mir.instructions.items(.data)[inst].rrr;
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switch (tag) {
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.mul => try emit.writeInstruction(Instruction.mul(rrr.rd, rrr.rn, rrr.rm)),
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.smulh => try emit.writeInstruction(Instruction.smulh(rrr.rd, rrr.rn, rrr.rm)),
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.smull => try emit.writeInstruction(Instruction.smull(rrr.rd, rrr.rn, rrr.rm)),
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.umulh => try emit.writeInstruction(Instruction.umulh(rrr.rd, rrr.rn, rrr.rm)),
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.umull => try emit.writeInstruction(Instruction.umull(rrr.rd, rrr.rn, rrr.rm)),
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.mul,
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.smulh,
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.smull,
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.umulh,
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.umull,
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=> {
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const rrr = emit.mir.instructions.items(.data)[inst].rrr;
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switch (tag) {
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.mul => try emit.writeInstruction(Instruction.mul(rrr.rd, rrr.rn, rrr.rm)),
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.smulh => try emit.writeInstruction(Instruction.smulh(rrr.rd, rrr.rn, rrr.rm)),
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.smull => try emit.writeInstruction(Instruction.smull(rrr.rd, rrr.rn, rrr.rm)),
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.umulh => try emit.writeInstruction(Instruction.umulh(rrr.rd, rrr.rn, rrr.rm)),
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.umull => try emit.writeInstruction(Instruction.umull(rrr.rd, rrr.rn, rrr.rm)),
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else => unreachable,
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}
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},
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.msub => {
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const rrrr = emit.mir.instructions.items(.data)[inst].rrrr;
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switch (tag) {
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.msub => try emit.writeInstruction(Instruction.msub(rrrr.rd, rrrr.rn, rrrr.rm, rrrr.ra)),
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else => unreachable,
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}
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},
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else => unreachable,
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}
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}
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@ -148,6 +148,8 @@ pub const Inst = struct {
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movk,
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/// Move wide with zero
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movz,
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/// Multiply-subtract
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msub,
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/// Multiply
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mul,
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/// Bitwise NOT
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@ -446,6 +448,15 @@ pub const Inst = struct {
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rn: Register,
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offset: bits.Instruction.LoadStorePairOffset,
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},
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/// Four registers
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///
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/// Used by e.g. msub
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rrrr: struct {
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rd: Register,
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rn: Register,
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rm: Register,
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ra: Register,
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},
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/// Debug info: line and column
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///
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/// Used by e.g. dbg_line
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