diff --git a/lib/std/Target/spirv.zig b/lib/std/Target/spirv.zig
index f45f9a6358..ca83ad2d26 100644
--- a/lib/std/Target/spirv.zig
+++ b/lib/std/Target/spirv.zig
@@ -17,6 +17,7 @@ pub const Feature = enum {
     float64,
     matrix,
     storage_push_constant16,
+    arbitrary_precision_integers,
     kernel,
     addresses,
     generic_pointer,
@@ -105,6 +106,11 @@ pub const all_features = blk: {
         .description = "Enable SPV_KHR_16bit_storage extension and the StoragePushConstant16 capability",
         .dependencies = featureSet(&[_]Feature{.v1_3}),
     };
+    result[@intFromEnum(Feature.arbitrary_precision_integers)] = .{
+        .llvm_name = null,
+        .description = "Enable SPV_INTEL_arbitrary_precision_integers extension and the ArbitraryPrecisionIntegersINTEL capability",
+        .dependencies = featureSet(&[_]Feature{ .v1_5, .int8, .int16 }),
+    };
     result[@intFromEnum(Feature.kernel)] = .{
         .llvm_name = null,
         .description = "Enable Kernel capability",
diff --git a/src/codegen/spirv.zig b/src/codegen/spirv.zig
index 3a00a05823..7fcbc66e82 100644
--- a/src/codegen/spirv.zig
+++ b/src/codegen/spirv.zig
@@ -581,13 +581,13 @@ const NavGen = struct {
     /// that size. In this case, multiple elements of the largest type should be used.
     /// The backing type will be chosen as the smallest supported integer larger or equal to it in number of bits.
     /// The result is valid to be used with OpTypeInt.
-    /// TODO: The extension SPV_INTEL_arbitrary_precision_integers allows any integer size (at least up to 32 bits).
-    /// TODO: This probably needs an ABI-version as well (especially in combination with SPV_INTEL_arbitrary_precision_integers).
     /// TODO: Should the result of this function be cached?
     fn backingIntBits(self: *NavGen, bits: u16) ?u16 {
         // The backend will never be asked to compiler a 0-bit integer, so we won't have to handle those in this function.
         assert(bits != 0);
 
+        if (self.spv.hasFeature(.arbitrary_precision_integers) and bits <= 32) return bits;
+
         // 8, 16 and 64-bit integers require the Int8, Int16 and Inr64 capabilities respectively.
         // 32-bit integers are always supported (see spec, 2.16.1, Data rules).
         const ints = [_]struct { bits: u16, feature: ?Target.spirv.Feature }{
diff --git a/src/codegen/spirv/Module.zig b/src/codegen/spirv/Module.zig
index f7d32ba178..6dc0e5842a 100644
--- a/src/codegen/spirv/Module.zig
+++ b/src/codegen/spirv/Module.zig
@@ -343,6 +343,10 @@ pub fn finalize(self: *Module, a: Allocator) ![]Word {
                     try self.addExtension("SPV_KHR_16bit_storage");
                     try self.addCapability(.StoragePushConstant16);
                 },
+                .arbitrary_precision_integers => {
+                    try self.addExtension("SPV_INTEL_arbitrary_precision_integers");
+                    try self.addCapability(.ArbitraryPrecisionIntegersINTEL);
+                },
                 .addresses => try self.addCapability(.Addresses),
                 // Kernel
                 .kernel => try self.addCapability(.Kernel),
diff --git a/test/behavior/vector.zig b/test/behavior/vector.zig
index df372be1ad..2d4c92d6fd 100644
--- a/test/behavior/vector.zig
+++ b/test/behavior/vector.zig
@@ -11,7 +11,6 @@ test "implicit cast vector to array - bool" {
     if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
-    if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
 
     const S = struct {
         fn doTheTest() !void {
@@ -30,7 +29,6 @@ test "vector wrap operators" {
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
-    if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_x86_64 and
         !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;