From 46527292178d64daa9f81be3eef378d78d254b5d Mon Sep 17 00:00:00 2001
From: xdBronch <51252236+xdBronch@users.noreply.github.com>
Date: Sat, 13 May 2023 06:21:49 -0400
Subject: [PATCH] std.simd.suggestVectorSizeForCpu: fix missing argument in
 body

---
 lib/std/simd.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/std/simd.zig b/lib/std/simd.zig
index 905925fb78..4ccdac6c1e 100644
--- a/lib/std/simd.zig
+++ b/lib/std/simd.zig
@@ -12,7 +12,7 @@ pub fn suggestVectorSizeForCpu(comptime T: type, comptime cpu: std.Target.Cpu) ?
     const element_bit_size = @max(8, std.math.ceilPowerOfTwo(u16, @bitSizeOf(T)) catch unreachable);
     const vector_bit_size: u16 = blk: {
         if (cpu.arch.isX86()) {
-            if (T == bool and std.Target.x86.featureSetHas(.prefer_mask_registers)) return 64;
+            if (T == bool and std.Target.x86.featureSetHas(cpu.features, .prefer_mask_registers)) return 64;
             if (std.Target.x86.featureSetHas(cpu.features, .avx512f) and !std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .prefer_128_bit })) break :blk 512;
             if (std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .avx2 }) and !std.Target.x86.featureSetHas(cpu.features, .prefer_128_bit)) break :blk 256;
             if (std.Target.x86.featureSetHas(cpu.features, .sse)) break :blk 128;