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AstGen: fix src loc for invalid switch expression rls coercions
This commit is contained in:
Jacob Young
parent
ce7acf1296
commit
41575fa868
167
src/AstGen.zig
167
src/AstGen.zig
@ -7178,7 +7178,8 @@ fn switchExpr(
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try astgen.extra.ensureUnusedCapacity(gpa, @typeInfo(Zir.Inst.SwitchBlock).Struct.fields.len +
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@intFromBool(multi_cases_len != 0) +
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@intFromBool(any_has_tag_capture) +
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payloads.items.len - case_table_end);
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payloads.items.len - case_table_end +
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(case_table_end - case_table_start) * @typeInfo(Zir.Inst.As).Struct.fields.len);
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const payload_index = astgen.addExtraAssumeCapacity(Zir.Inst.SwitchBlock{
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.operand = raw_operand,
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@ -7205,82 +7206,108 @@ fn switchExpr(
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zir_datas[switch_block].pl_node.payload_index = payload_index;
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const strat = ri.rl.strategy(&block_scope);
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for (payloads.items[case_table_start..case_table_end], 0..) |start_index, i| {
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var body_len_index = start_index;
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var end_index = start_index;
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const table_index = case_table_start + i;
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if (table_index < scalar_case_table) {
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end_index += 1;
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} else if (table_index < multi_case_table) {
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body_len_index += 1;
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end_index += 2;
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} else {
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body_len_index += 2;
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const items_len = payloads.items[start_index];
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const ranges_len = payloads.items[start_index + 1];
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end_index += 3 + items_len + 2 * ranges_len;
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}
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inline for (.{ .body, .breaks }) |pass| {
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for (payloads.items[case_table_start..case_table_end], 0..) |start_index, i| {
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var body_len_index = start_index;
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var end_index = start_index;
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const table_index = case_table_start + i;
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if (table_index < scalar_case_table) {
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end_index += 1;
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} else if (table_index < multi_case_table) {
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body_len_index += 1;
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end_index += 2;
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} else {
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body_len_index += 2;
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const items_len = payloads.items[start_index];
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const ranges_len = payloads.items[start_index + 1];
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end_index += 3 + items_len + 2 * ranges_len;
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}
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const body_len = @as(Zir.Inst.SwitchBlock.ProngInfo, @bitCast(payloads.items[body_len_index])).body_len;
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end_index += body_len;
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const prong_info: Zir.Inst.SwitchBlock.ProngInfo = @bitCast(payloads.items[body_len_index]);
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end_index += prong_info.body_len;
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switch (strat.tag) {
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.break_operand => blk: {
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// Switch expressions return `true` for `nodeMayNeedMemoryLocation` thus
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// `elide_store_to_block_ptr_instructions` will either be true,
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// or all prongs are noreturn.
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if (!strat.elide_store_to_block_ptr_instructions)
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break :blk;
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switch (strat.tag) {
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.break_operand => blk: {
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// Switch expressions return `true` for `nodeMayNeedMemoryLocation` thus
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// `elide_store_to_block_ptr_instructions` will either be true,
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// or all prongs are noreturn.
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if (!strat.elide_store_to_block_ptr_instructions)
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break :blk;
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// There will necessarily be a store_to_block_ptr for
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// all prongs, except for prongs that ended with a noreturn instruction.
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// Elide all the `store_to_block_ptr` instructions.
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// There will necessarily be a store_to_block_ptr for
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// all prongs, except for prongs that ended with a noreturn instruction.
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// Elide all the `store_to_block_ptr` instructions.
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// The break instructions need to have their operands coerced if the
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// switch's result location is a `ty`. In this case we overwrite the
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// `store_to_block_ptr` instruction with an `as` instruction and repurpose
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// it as the break operand.
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if (body_len < 2)
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break :blk;
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// The break instructions need to have their operands coerced if the
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// switch's result location is a `ty`. In this case we overwrite the
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// `store_to_block_ptr` instruction with an `as` instruction and repurpose
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// it as the break operand.
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if (prong_info.body_len < 2)
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break :blk;
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var store_index = end_index - 2;
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while (true) : (store_index -= 1) switch (zir_tags[payloads.items[store_index]]) {
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.dbg_block_end, .dbg_block_begin, .dbg_stmt, .dbg_var_val, .dbg_var_ptr => {},
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else => break,
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};
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const store_inst = payloads.items[store_index];
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if (zir_tags[store_inst] != .store_to_block_ptr or
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zir_datas[store_inst].bin.lhs != block_scope.rl_ptr)
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break :blk;
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const break_inst = payloads.items[end_index - 1];
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if (block_scope.rl_ty_inst != .none) {
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zir_tags[store_inst] = .as;
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zir_datas[store_inst].bin = .{
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.lhs = block_scope.rl_ty_inst,
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.rhs = zir_datas[break_inst].@"break".operand,
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var store_index = end_index - 2;
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while (true) : (store_index -= 1) switch (zir_tags[payloads.items[store_index]]) {
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.dbg_block_end, .dbg_block_begin, .dbg_stmt, .dbg_var_val, .dbg_var_ptr => {},
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else => break,
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};
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zir_datas[break_inst].@"break".operand = indexToRef(store_inst);
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} else {
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payloads.items[body_len_index] -= 1;
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astgen.extra.appendSliceAssumeCapacity(payloads.items[start_index .. end_index - 2]);
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astgen.extra.appendAssumeCapacity(break_inst);
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continue;
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}
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},
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.break_void => {
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assert(!strat.elide_store_to_block_ptr_instructions);
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const last_inst = payloads.items[end_index - 1];
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if (zir_tags[last_inst] == .@"break") {
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const break_data = &zir_datas[last_inst].@"break";
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const block_inst = astgen.extra.items[
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break_data.payload_index + std.meta.fieldIndex(Zir.Inst.Break, "block_inst").?
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];
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if (block_inst == switch_block) break_data.operand = .void_value;
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}
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},
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}
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const store_inst = payloads.items[store_index];
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if (zir_tags[store_inst] != .store_to_block_ptr or
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zir_datas[store_inst].bin.lhs != block_scope.rl_ptr)
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break :blk;
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const break_inst = payloads.items[end_index - 1];
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if (block_scope.rl_ty_inst != .none) {
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if (pass == .breaks) {
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const break_data = &zir_datas[break_inst].@"break";
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const break_src: i32 = @bitCast(astgen.extra.items[
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break_data.payload_index +
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std.meta.fieldIndex(Zir.Inst.Break, "operand_src_node").?
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]);
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if (break_src == Zir.Inst.Break.no_src_node) {
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zir_tags[store_inst] = .as;
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zir_datas[store_inst].bin = .{
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.lhs = block_scope.rl_ty_inst,
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.rhs = break_data.operand,
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};
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} else {
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zir_tags[store_inst] = .as_node;
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zir_datas[store_inst] = .{ .pl_node = .{
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.src_node = break_src,
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.payload_index = astgen.addExtraAssumeCapacity(Zir.Inst.As{
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.dest_type = block_scope.rl_ty_inst,
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.operand = break_data.operand,
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}),
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} };
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}
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break_data.operand = indexToRef(store_inst);
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}
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} else {
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if (pass == .body) {
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payloads.items[body_len_index] -= 1;
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astgen.extra.appendSliceAssumeCapacity(
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payloads.items[start_index .. end_index - 2],
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);
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astgen.extra.appendAssumeCapacity(break_inst);
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}
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continue;
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}
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},
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.break_void => if (pass == .breaks) {
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assert(!strat.elide_store_to_block_ptr_instructions);
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const last_inst = payloads.items[end_index - 1];
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if (zir_tags[last_inst] == .@"break") {
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const break_data = &zir_datas[last_inst].@"break";
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const block_inst = astgen.extra.items[
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break_data.payload_index +
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std.meta.fieldIndex(Zir.Inst.Break, "block_inst").?
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];
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if (block_inst == switch_block) break_data.operand = .void_value;
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}
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},
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}
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astgen.extra.appendSliceAssumeCapacity(payloads.items[start_index..end_index]);
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if (pass == .body)
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astgen.extra.appendSliceAssumeCapacity(payloads.items[start_index..end_index]);
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}
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}
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const block_ref = indexToRef(switch_block);
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@ -0,0 +1,46 @@
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const Enum = enum(u8) { first, second, _ };
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export fn invalidFirstProng(enum_value: Enum) u8 {
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const result: u8 = switch (enum_value) {
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.first => 256,
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.second => 0,
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else => 0,
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};
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return result;
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}
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export fn invalidSecondProng(enum_value: Enum) u8 {
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const result: u8 = switch (enum_value) {
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.first => 0,
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.second => 256,
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_ => 0,
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};
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return result;
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}
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export fn invalidElseProng(enum_value: Enum) u8 {
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const result: u8 = switch (enum_value) {
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.first => 0,
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.second => 0,
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else => 256,
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};
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return result;
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}
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export fn invalidNonExhaustiveProng(enum_value: Enum) u8 {
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const result: u8 = switch (enum_value) {
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.first => 0,
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.second => 0,
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_ => 256,
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};
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return result;
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}
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// error
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// backend=stage2
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// target=native
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//
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// :5:19: error: type 'u8' cannot represent integer value '256'
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// :15:20: error: type 'u8' cannot represent integer value '256'
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// :25:17: error: type 'u8' cannot represent integer value '256'
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// :34:14: error: type 'u8' cannot represent integer value '256'
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