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stage1: avoid wasting padding with IR instruction tag

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For stage1 ZIR instructions and stage1 AIR instructions, the instruction
op code was taking up 8 bytes due to padding even though it only needed
1 byte. This commit reduces the ref_count field from uint32_t to
uint16_t because the code only really cares if instructions are
referenced at all, not how many times they are referenced. With the
ref_count field reduced to uint16_t the uint8_t op code is now placed in
the freed up space.

Empirically, this saves 382 MiB of peak RAM usage when building the
self-hosted compiler, which is a reduction of 5%. Consequently this
resulted in a 3% reduction of cache-misses when building the self-hosted
compiler.

This was @SpexGuy's idea, committed by me because we tested it on my
computer.
This commit is contained in:
Andrew Kelley 2021-07-10 15:27:33 -07:00
parent b9e896d7b0
commit 40764650af
1 changed files with 5 additions and 6 deletions
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11
src/stage1/all_types.hpp
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@ -2475,7 +2475,7 @@ struct IrBasicBlockGen {
// Src instructions are generated by ir_gen_* functions in ir.cpp from AST. // Src instructions are generated by ir_gen_* functions in ir.cpp from AST.
// ir_analyze_* functions consume Src instructions and produce Gen instructions. // ir_analyze_* functions consume Src instructions and produce Gen instructions.
// Src instructions do not have type information; Gen instructions do. // Src instructions do not have type information; Gen instructions do.
enum IrInstSrcId { enum IrInstSrcId : uint8_t {
IrInstSrcIdInvalid, IrInstSrcIdInvalid,
IrInstSrcIdDeclVar, IrInstSrcIdDeclVar,
IrInstSrcIdBr, IrInstSrcIdBr,
@ -2620,7 +2620,7 @@ enum IrInstSrcId {
// ir_render_* functions in codegen.cpp consume Gen instructions and produce LLVM IR. // ir_render_* functions in codegen.cpp consume Gen instructions and produce LLVM IR.
// Src instructions do not have type information; Gen instructions do. // Src instructions do not have type information; Gen instructions do.
enum IrInstGenId { enum IrInstGenId : uint8_t {
IrInstGenIdInvalid, IrInstGenIdInvalid,
IrInstGenIdDeclVar, IrInstGenIdDeclVar,
IrInstGenIdBr, IrInstGenIdBr,
@ -2714,14 +2714,13 @@ enum IrInstGenId {
}; };
struct IrInstSrc { struct IrInstSrc {
uint32_t ref_count; IrInstSrcId id;
uint16_t ref_count;
uint32_t debug_id; uint32_t debug_id;
Scope *scope; Scope *scope;
AstNode *source_node; AstNode *source_node;
IrInstSrcId id;
// When analyzing IR, instructions that point to this instruction in the "old ir" // When analyzing IR, instructions that point to this instruction in the "old ir"
// can find the instruction that corresponds to this value in the "new ir" // can find the instruction that corresponds to this value in the "new ir"
// with this child field. // with this child field.
@ -2737,7 +2736,7 @@ struct IrInstGen {
IrInstGenId id; IrInstGenId id;
// if ref_count is zero and the instruction has no side effects, // if ref_count is zero and the instruction has no side effects,
// the instruction can be omitted in codegen // the instruction can be omitted in codegen
uint32_t ref_count; uint16_t ref_count;
uint32_t debug_id; uint32_t debug_id;
Scope *scope; Scope *scope;