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Merge pull request #11658 from koachan/sparc64-codegen
stage2: sparc64: Make basic test harness run
This commit is contained in:
Jakub Konka
GitHub
commit
3fde14035b
File diff suppressed because it is too large
Load Diff
@ -8,6 +8,7 @@ const link = @import("../../link.zig");
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const Module = @import("../../Module.zig");
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const ErrorMsg = Module.ErrorMsg;
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const Liveness = @import("../../Liveness.zig");
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const log = std.log.scoped(.sparcv9_emit);
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const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
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const DW = std.dwarf;
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const leb128 = std.leb;
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@ -31,16 +32,44 @@ prev_di_column: u32,
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/// Relative to the beginning of `code`.
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prev_di_pc: usize,
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/// The branch type of every branch
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branch_types: std.AutoHashMapUnmanaged(Mir.Inst.Index, BranchType) = .{},
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/// For every forward branch, maps the target instruction to a list of
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/// branches which branch to this target instruction
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branch_forward_origins: std.AutoHashMapUnmanaged(Mir.Inst.Index, std.ArrayListUnmanaged(Mir.Inst.Index)) = .{},
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/// For backward branches: stores the code offset of the target
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/// instruction
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///
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/// For forward branches: stores the code offset of the branch
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/// instruction
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code_offset_mapping: std.AutoHashMapUnmanaged(Mir.Inst.Index, usize) = .{},
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const InnerError = error{
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OutOfMemory,
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EmitFail,
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};
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const BranchType = enum {
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bpcc,
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bpr,
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fn default(tag: Mir.Inst.Tag) BranchType {
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return switch (tag) {
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.bpcc => .bpcc,
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.bpr => .bpr,
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else => unreachable,
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};
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}
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};
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pub fn emitMir(
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emit: *Emit,
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) InnerError!void {
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const mir_tags = emit.mir.instructions.items(.tag);
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// Convert absolute addresses into offsets and
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// find smallest lowerings for branch instructions
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try emit.lowerBranches();
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// Emit machine code
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for (mir_tags) |tag, index| {
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const inst = @intCast(u32, index);
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@ -51,7 +80,8 @@ pub fn emitMir(
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.add => try emit.mirArithmetic3Op(inst),
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.bpcc => @panic("TODO implement sparc64 bpcc"),
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.bpr => try emit.mirConditionalBranch(inst),
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.bpcc => try emit.mirConditionalBranch(inst),
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.call => @panic("TODO implement sparc64 call"),
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@ -64,6 +94,8 @@ pub fn emitMir(
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.@"or" => try emit.mirArithmetic3Op(inst),
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.mulx => try emit.mirArithmetic3Op(inst),
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.nop => try emit.mirNop(),
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.@"return" => try emit.mirArithmetic2Op(inst),
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@ -73,7 +105,12 @@ pub fn emitMir(
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.sethi => try emit.mirSethi(inst),
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.sll => @panic("TODO implement sparc64 sll"),
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.srl => @panic("TODO implement sparc64 srl"),
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.sra => @panic("TODO implement sparc64 sra"),
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.sllx => @panic("TODO implement sparc64 sllx"),
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.srlx => @panic("TODO implement sparc64 srlx"),
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.srax => @panic("TODO implement sparc64 srax"),
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.stb => try emit.mirArithmetic3Op(inst),
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.sth => try emit.mirArithmetic3Op(inst),
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@ -81,6 +118,7 @@ pub fn emitMir(
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.stx => try emit.mirArithmetic3Op(inst),
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.sub => try emit.mirArithmetic3Op(inst),
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.subcc => try emit.mirArithmetic3Op(inst),
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.tcc => try emit.mirTrap(inst),
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}
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@ -88,6 +126,14 @@ pub fn emitMir(
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}
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pub fn deinit(emit: *Emit) void {
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var iter = emit.branch_forward_origins.valueIterator();
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while (iter.next()) |origin_list| {
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origin_list.deinit(emit.bin_file.allocator);
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}
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emit.branch_types.deinit(emit.bin_file.allocator);
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emit.branch_forward_origins.deinit(emit.bin_file.allocator);
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emit.code_offset_mapping.deinit(emit.bin_file.allocator);
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emit.* = undefined;
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}
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@ -161,6 +207,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
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.lduw => try emit.writeInstruction(Instruction.lduw(i13, rs1, imm, rd)),
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.ldx => try emit.writeInstruction(Instruction.ldx(i13, rs1, imm, rd)),
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.@"or" => try emit.writeInstruction(Instruction.@"or"(i13, rs1, imm, rd)),
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.mulx => try emit.writeInstruction(Instruction.mulx(i13, rs1, imm, rd)),
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.save => try emit.writeInstruction(Instruction.save(i13, rs1, imm, rd)),
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.restore => try emit.writeInstruction(Instruction.restore(i13, rs1, imm, rd)),
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.stb => try emit.writeInstruction(Instruction.stb(i13, rs1, imm, rd)),
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@ -168,6 +215,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
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.stw => try emit.writeInstruction(Instruction.stw(i13, rs1, imm, rd)),
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.stx => try emit.writeInstruction(Instruction.stx(i13, rs1, imm, rd)),
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.sub => try emit.writeInstruction(Instruction.sub(i13, rs1, imm, rd)),
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.subcc => try emit.writeInstruction(Instruction.subcc(i13, rs1, imm, rd)),
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else => unreachable,
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}
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} else {
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@ -180,6 +228,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
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.lduw => try emit.writeInstruction(Instruction.lduw(Register, rs1, rs2, rd)),
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.ldx => try emit.writeInstruction(Instruction.ldx(Register, rs1, rs2, rd)),
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.@"or" => try emit.writeInstruction(Instruction.@"or"(Register, rs1, rs2, rd)),
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.mulx => try emit.writeInstruction(Instruction.mulx(Register, rs1, rs2, rd)),
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.save => try emit.writeInstruction(Instruction.save(Register, rs1, rs2, rd)),
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.restore => try emit.writeInstruction(Instruction.restore(Register, rs1, rs2, rd)),
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.stb => try emit.writeInstruction(Instruction.stb(Register, rs1, rs2, rd)),
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@ -187,11 +236,56 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
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.stw => try emit.writeInstruction(Instruction.stw(Register, rs1, rs2, rd)),
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.stx => try emit.writeInstruction(Instruction.stx(Register, rs1, rs2, rd)),
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.sub => try emit.writeInstruction(Instruction.sub(Register, rs1, rs2, rd)),
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.subcc => try emit.writeInstruction(Instruction.subcc(Register, rs1, rs2, rd)),
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else => unreachable,
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}
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}
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}
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fn mirConditionalBranch(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const branch_type = emit.branch_types.get(inst).?;
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switch (branch_type) {
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.bpcc => switch (tag) {
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.bpcc => {
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const branch_predict_int = emit.mir.instructions.items(.data)[inst].branch_predict_int;
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const offset = @intCast(i64, emit.code_offset_mapping.get(branch_predict_int.inst).?) - @intCast(i64, emit.code.items.len);
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log.debug("mirConditionalBranch: {} offset={}", .{ inst, offset });
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try emit.writeInstruction(
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Instruction.bpcc(
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branch_predict_int.cond,
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branch_predict_int.annul,
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branch_predict_int.pt,
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branch_predict_int.ccr,
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@intCast(i21, offset),
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),
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);
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},
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else => unreachable,
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},
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.bpr => switch (tag) {
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.bpr => {
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const branch_predict_reg = emit.mir.instructions.items(.data)[inst].branch_predict_reg;
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const offset = @intCast(i64, emit.code_offset_mapping.get(branch_predict_reg.inst).?) - @intCast(i64, emit.code.items.len);
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log.debug("mirConditionalBranch: {} offset={}", .{ inst, offset });
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try emit.writeInstruction(
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Instruction.bpr(
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branch_predict_reg.cond,
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branch_predict_reg.annul,
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branch_predict_reg.pt,
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branch_predict_reg.rs1,
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@intCast(i18, offset),
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),
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);
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},
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else => unreachable,
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},
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}
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}
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fn mirNop(emit: *Emit) !void {
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try emit.writeInstruction(Instruction.nop());
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}
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@ -232,6 +326,16 @@ fn mirTrap(emit: *Emit, inst: Mir.Inst.Index) !void {
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// Common helper functions
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fn branchTarget(emit: *Emit, inst: Mir.Inst.Index) Mir.Inst.Index {
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const tag = emit.mir.instructions.items(.tag)[inst];
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switch (tag) {
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.bpcc => return emit.mir.instructions.items(.data)[inst].branch_predict_int.inst,
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.bpr => return emit.mir.instructions.items(.data)[inst].branch_predict_reg.inst,
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else => unreachable,
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}
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}
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fn dbgAdvancePCAndLine(emit: *Emit, line: u32, column: u32) !void {
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const delta_line = @intCast(i32, line) - @intCast(i32, emit.prev_di_line);
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const delta_pc: usize = emit.code.items.len - emit.prev_di_pc;
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@ -264,6 +368,164 @@ fn fail(emit: *Emit, comptime format: []const u8, args: anytype) InnerError {
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return error.EmitFail;
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}
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fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
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const tag = emit.mir.instructions.items(.tag)[inst];
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switch (tag) {
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.dbg_line,
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.dbg_epilogue_begin,
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.dbg_prologue_end,
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=> return 0,
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// Currently Mir instructions always map to single machine instruction.
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else => return 4,
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}
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}
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fn isBranch(tag: Mir.Inst.Tag) bool {
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return switch (tag) {
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.bpcc => true,
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.bpr => true,
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else => false,
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};
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}
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fn lowerBranches(emit: *Emit) !void {
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const mir_tags = emit.mir.instructions.items(.tag);
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const allocator = emit.bin_file.allocator;
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// First pass: Note down all branches and their target
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// instructions, i.e. populate branch_types,
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// branch_forward_origins, and code_offset_mapping
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//
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// TODO optimization opportunity: do this in codegen while
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// generating MIR
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for (mir_tags) |tag, index| {
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const inst = @intCast(u32, index);
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if (isBranch(tag)) {
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const target_inst = emit.branchTarget(inst);
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// Remember this branch instruction
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try emit.branch_types.put(allocator, inst, BranchType.default(tag));
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// Forward branches require some extra stuff: We only
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// know their offset once we arrive at the target
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// instruction. Therefore, we need to be able to
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// access the branch instruction when we visit the
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// target instruction in order to manipulate its type
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// etc.
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if (target_inst > inst) {
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// Remember the branch instruction index
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try emit.code_offset_mapping.put(allocator, inst, 0);
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if (emit.branch_forward_origins.getPtr(target_inst)) |origin_list| {
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try origin_list.append(allocator, inst);
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} else {
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var origin_list: std.ArrayListUnmanaged(Mir.Inst.Index) = .{};
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try origin_list.append(allocator, inst);
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try emit.branch_forward_origins.put(allocator, target_inst, origin_list);
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}
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}
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// Remember the target instruction index so that we
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// update the real code offset in all future passes
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//
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// putNoClobber may not be used as the put operation
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// may clobber the entry when multiple branches branch
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// to the same target instruction
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try emit.code_offset_mapping.put(allocator, target_inst, 0);
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}
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}
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// Further passes: Until all branches are lowered, interate
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// through all instructions and calculate new offsets and
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// potentially new branch types
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var all_branches_lowered = false;
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while (!all_branches_lowered) {
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all_branches_lowered = true;
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var current_code_offset: usize = 0;
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for (mir_tags) |tag, index| {
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const inst = @intCast(u32, index);
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// If this instruction contained in the code offset
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// mapping (when it is a target of a branch or if it is a
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// forward branch), update the code offset
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if (emit.code_offset_mapping.getPtr(inst)) |offset| {
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offset.* = current_code_offset;
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}
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// If this instruction is a backward branch, calculate the
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// offset, which may potentially update the branch type
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if (isBranch(tag)) {
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const target_inst = emit.branchTarget(inst);
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if (target_inst < inst) {
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const target_offset = emit.code_offset_mapping.get(target_inst).?;
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const offset = @intCast(i64, target_offset) - @intCast(i64, current_code_offset);
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const branch_type = emit.branch_types.getPtr(inst).?;
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const optimal_branch_type = try emit.optimalBranchType(tag, offset);
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if (branch_type.* != optimal_branch_type) {
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branch_type.* = optimal_branch_type;
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all_branches_lowered = false;
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}
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log.debug("lowerBranches: branch {} has offset {}", .{ inst, offset });
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}
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}
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// If this instruction is the target of one or more
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// forward branches, calculate the offset, which may
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// potentially update the branch type
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if (emit.branch_forward_origins.get(inst)) |origin_list| {
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for (origin_list.items) |forward_branch_inst| {
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const branch_tag = emit.mir.instructions.items(.tag)[forward_branch_inst];
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const forward_branch_inst_offset = emit.code_offset_mapping.get(forward_branch_inst).?;
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const offset = @intCast(i64, current_code_offset) - @intCast(i64, forward_branch_inst_offset);
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const branch_type = emit.branch_types.getPtr(forward_branch_inst).?;
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const optimal_branch_type = try emit.optimalBranchType(branch_tag, offset);
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if (branch_type.* != optimal_branch_type) {
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branch_type.* = optimal_branch_type;
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all_branches_lowered = false;
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}
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log.debug("lowerBranches: branch {} has offset {}", .{ forward_branch_inst, offset });
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}
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}
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// Increment code offset
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current_code_offset += emit.instructionSize(inst);
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}
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}
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}
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fn optimalBranchType(emit: *Emit, tag: Mir.Inst.Tag, offset: i64) !BranchType {
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assert(offset & 0b11 == 0);
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switch (tag) {
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// TODO use the following strategy to implement long branches:
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// - Negate the conditional and target of the original instruction;
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// - In the space immediately after the branch, load
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// the address of the original target, preferrably in
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// a PC-relative way, into %o7; and
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// - jmpl %o7 + %g0, %g0
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.bpcc => {
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if (std.math.cast(i21, offset)) |_| {
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return BranchType.bpcc;
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} else |_| {
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return emit.fail("TODO support BPcc branches larger than +-1 MiB", .{});
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}
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},
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.bpr => {
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if (std.math.cast(i18, offset)) |_| {
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return BranchType.bpr;
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} else |_| {
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return emit.fail("TODO support BPr branches larger than +-128 KiB", .{});
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}
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},
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else => unreachable,
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}
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}
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fn writeInstruction(emit: *Emit, instruction: Instruction) !void {
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// SPARCv9 instructions are always arranged in BE regardless of the
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// endianness mode the CPU is running in (Section 3.1 of the ISA specification).
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@ -43,8 +43,12 @@ pub const Inst = struct {
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// TODO add other operations.
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add,
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/// A.3 Branch on Integer Register with Prediction (BPr)
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/// This uses the branch_predict_reg field.
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bpr,
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/// A.7 Branch on Integer Condition Codes with Prediction (BPcc)
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/// This uses the branch_predict field.
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/// This uses the branch_predict_int field.
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bpcc,
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/// A.8 Call and Link
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@ -70,6 +74,11 @@ pub const Inst = struct {
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// TODO add other operations.
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@"or",
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/// A.37 Multiply and Divide (64-bit)
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/// This uses the arithmetic_3op field.
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// TODO add other operations.
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mulx,
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/// A.40 No Operation
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/// This uses the nop field.
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nop,
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@ -89,8 +98,12 @@ pub const Inst = struct {
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/// A.49 Shift
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/// This uses the shift field.
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// TODO add other operations.
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sll,
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srl,
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sra,
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sllx,
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srlx,
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srax,
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/// A.54 Store Integer
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/// This uses the arithmetic_3op field.
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@ -106,10 +119,15 @@ pub const Inst = struct {
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/// This uses the arithmetic_3op field.
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// TODO add other operations.
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sub,
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subcc,
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/// A.61 Trap on Integer Condition Codes (Tcc)
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/// This uses the trap field.
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tcc,
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// TODO add synthetic instructions
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||||
// TODO add cmp synthetic instruction to avoid wasting a register when
|
||||
// comparing with subcc
|
||||
};
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|
||||
/// The position of an MIR instruction within the `Mir` instructions array.
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@ -164,13 +182,23 @@ pub const Inst = struct {
|
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link: Register = .o7,
|
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},
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||||
|
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/// Branch with prediction.
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/// Branch with prediction, checking the integer status code
|
||||
/// Used by e.g. bpcc
|
||||
branch_predict: struct {
|
||||
branch_predict_int: struct {
|
||||
annul: bool = false,
|
||||
pt: bool = true,
|
||||
ccr: Instruction.CCR,
|
||||
cond: Instruction.Condition,
|
||||
cond: Instruction.ICondition,
|
||||
inst: Index,
|
||||
},
|
||||
|
||||
/// Branch with prediction, comparing a register's content with zero
|
||||
/// Used by e.g. bpr
|
||||
branch_predict_reg: struct {
|
||||
annul: bool = false,
|
||||
pt: bool = true,
|
||||
cond: Instruction.RCondition,
|
||||
rs1: Register,
|
||||
inst: Index,
|
||||
},
|
||||
|
||||
@ -191,7 +219,7 @@ pub const Inst = struct {
|
||||
/// if is_imm true then it uses the imm field of rs2_or_imm,
|
||||
/// otherwise it uses rs2 field.
|
||||
///
|
||||
/// Used by e.g. add, sub
|
||||
/// Used by e.g. sllx
|
||||
shift: struct {
|
||||
is_imm: bool,
|
||||
width: Instruction.ShiftWidth,
|
||||
@ -210,7 +238,7 @@ pub const Inst = struct {
|
||||
/// Used by e.g. tcc
|
||||
trap: struct {
|
||||
is_imm: bool = true,
|
||||
cond: Instruction.Condition,
|
||||
cond: Instruction.ICondition,
|
||||
ccr: Instruction.CCR = .icc,
|
||||
rs1: Register = .g0,
|
||||
rs2_or_imm: union {
|
||||
|
||||
@ -512,10 +512,172 @@ pub const Instruction = union(enum) {
|
||||
lookaside: bool = false,
|
||||
};
|
||||
|
||||
// TODO: Need to define an enum for `cond` values
|
||||
// This is kinda challenging since the cond values have different meanings
|
||||
// depending on whether it's operating on integer or FP CCR.
|
||||
pub const Condition = u4;
|
||||
// In SPARCv9, FP and integer comparison operations
|
||||
// are encoded differently.
|
||||
|
||||
pub const FCondition = enum(u4) {
|
||||
/// Branch Never
|
||||
nv,
|
||||
/// Branch on Not Equal
|
||||
ne,
|
||||
/// Branch on Less or Greater
|
||||
lg,
|
||||
/// Branch on Unordered or Less
|
||||
ul,
|
||||
/// Branch on Less
|
||||
lt,
|
||||
/// Branch on Unordered or Greater
|
||||
ug,
|
||||
/// Branch on Greater
|
||||
gt,
|
||||
/// Branch on Unordered
|
||||
un,
|
||||
/// Branch Always
|
||||
al,
|
||||
/// Branch on Equal
|
||||
eq,
|
||||
/// Branch on Unordered or Equal
|
||||
ue,
|
||||
/// Branch on Greater or Equal
|
||||
ge,
|
||||
/// Branch on Unordered or Greater or Equal
|
||||
uge,
|
||||
/// Branch on Less or Equal
|
||||
le,
|
||||
/// Branch on Unordered or Less or Equal
|
||||
ule,
|
||||
/// Branch on Ordered
|
||||
ord,
|
||||
|
||||
/// Converts a std.math.CompareOperator into a condition flag,
|
||||
/// i.e. returns the condition that is true iff the result of the
|
||||
/// comparison is true.
|
||||
pub fn fromCompareOperator(op: std.math.CompareOperator) FCondition {
|
||||
return switch (op) {
|
||||
.gte => .ge,
|
||||
.gt => .gt,
|
||||
.neq => .ne,
|
||||
.lt => .lt,
|
||||
.lte => .le,
|
||||
.eq => .eq,
|
||||
};
|
||||
}
|
||||
|
||||
/// Returns the condition which is true iff the given condition is
|
||||
/// false (if such a condition exists).
|
||||
pub fn negate(cond: FCondition) FCondition {
|
||||
return switch (cond) {
|
||||
.eq => .ne,
|
||||
.ne => .eq,
|
||||
.ge => .ul,
|
||||
.ul => .ge,
|
||||
.le => .ug,
|
||||
.ug => .le,
|
||||
.lt => .uge,
|
||||
.uge => .lt,
|
||||
.gt => .ule,
|
||||
.ule => .gt,
|
||||
.ue => .lg,
|
||||
.lg => .ue,
|
||||
.ord => .un,
|
||||
.un => .ord,
|
||||
.al => unreachable,
|
||||
.nv => unreachable,
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
pub const ICondition = enum(u4) {
|
||||
/// Branch Never
|
||||
nv,
|
||||
/// Branch on Equal
|
||||
eq,
|
||||
/// Branch on Less or Equal
|
||||
le,
|
||||
/// Branch on Less
|
||||
lt,
|
||||
/// Branch on Less or Equal Unsigned
|
||||
leu,
|
||||
/// Branch on Carry Set (Less than, Unsigned)
|
||||
cs,
|
||||
/// Branch on Negative
|
||||
neg,
|
||||
/// Branch on Overflow Set
|
||||
vs,
|
||||
/// Branch Always
|
||||
al,
|
||||
/// Branch on Not Equal
|
||||
ne,
|
||||
/// Branch on Greater
|
||||
gt,
|
||||
/// Branch on Greater or Equal
|
||||
ge,
|
||||
/// Branch on Greater Unsigned
|
||||
gu,
|
||||
/// Branch on Carry Clear (Greater Than or Equal, Unsigned)
|
||||
cc,
|
||||
/// Branch on Positive
|
||||
pos,
|
||||
/// Branch on Overflow Clear
|
||||
vc,
|
||||
|
||||
/// Converts a std.math.CompareOperator into a condition flag,
|
||||
/// i.e. returns the condition that is true iff the result of the
|
||||
/// comparison is true. Assumes signed comparison.
|
||||
pub fn fromCompareOperatorSigned(op: std.math.CompareOperator) ICondition {
|
||||
return switch (op) {
|
||||
.gte => .ge,
|
||||
.gt => .gt,
|
||||
.neq => .ne,
|
||||
.lt => .lt,
|
||||
.lte => .le,
|
||||
.eq => .eq,
|
||||
};
|
||||
}
|
||||
|
||||
/// Converts a std.math.CompareOperator into a condition flag,
|
||||
/// i.e. returns the condition that is true iff the result of the
|
||||
/// comparison is true. Assumes unsigned comparison.
|
||||
pub fn fromCompareOperatorUnsigned(op: std.math.CompareOperator) ICondition {
|
||||
return switch (op) {
|
||||
.gte => .cc,
|
||||
.gt => .gu,
|
||||
.neq => .ne,
|
||||
.lt => .cs,
|
||||
.lte => .le,
|
||||
.eq => .eq,
|
||||
};
|
||||
}
|
||||
|
||||
/// Returns the condition which is true iff the given condition is
|
||||
/// false (if such a condition exists).
|
||||
pub fn negate(cond: ICondition) ICondition {
|
||||
return switch (cond) {
|
||||
.eq => .ne,
|
||||
.ne => .eq,
|
||||
.cs => .cc,
|
||||
.cc => .cs,
|
||||
.neg => .pos,
|
||||
.pos => .neg,
|
||||
.vs => .vc,
|
||||
.vc => .vs,
|
||||
.gu => .leu,
|
||||
.leu => .gu,
|
||||
.ge => .lt,
|
||||
.lt => .ge,
|
||||
.gt => .le,
|
||||
.le => .gt,
|
||||
.al => unreachable,
|
||||
.nv => unreachable,
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
pub const Condition = packed union {
|
||||
fcond: FCondition,
|
||||
icond: ICondition,
|
||||
encoded: u4,
|
||||
};
|
||||
|
||||
pub fn toU32(self: Instruction) u32 {
|
||||
// TODO: Remove this once packed structs work.
|
||||
@ -593,7 +755,7 @@ pub const Instruction = union(enum) {
|
||||
return Instruction{
|
||||
.format_2b = .{
|
||||
.a = @boolToInt(annul),
|
||||
.cond = cond,
|
||||
.cond = cond.encoded,
|
||||
.op2 = op2,
|
||||
.disp22 = udisp_truncated,
|
||||
},
|
||||
@ -614,7 +776,7 @@ pub const Instruction = union(enum) {
|
||||
return Instruction{
|
||||
.format_2c = .{
|
||||
.a = @boolToInt(annul),
|
||||
.cond = cond,
|
||||
.cond = cond.encoded,
|
||||
.op2 = op2,
|
||||
.cc1 = ccr_cc1,
|
||||
.cc0 = ccr_cc0,
|
||||
@ -895,7 +1057,7 @@ pub const Instruction = union(enum) {
|
||||
.rd = rd.enc(),
|
||||
.op3 = op3,
|
||||
.cc2 = ccr_cc2,
|
||||
.cond = cond,
|
||||
.cond = cond.encoded,
|
||||
.cc1 = ccr_cc1,
|
||||
.cc0 = ccr_cc0,
|
||||
.rs2 = rs2.enc(),
|
||||
@ -912,7 +1074,7 @@ pub const Instruction = union(enum) {
|
||||
.rd = rd.enc(),
|
||||
.op3 = op3,
|
||||
.cc2 = ccr_cc2,
|
||||
.cond = cond,
|
||||
.cond = cond.encoded,
|
||||
.cc1 = ccr_cc1,
|
||||
.cc0 = ccr_cc0,
|
||||
.simm11 = @bitCast(u11, imm),
|
||||
@ -960,7 +1122,7 @@ pub const Instruction = union(enum) {
|
||||
.format_4g = .{
|
||||
.rd = rd.enc(),
|
||||
.op3 = op3,
|
||||
.cond = cond,
|
||||
.cond = cond.encoded,
|
||||
.opf_cc = opf_cc,
|
||||
.opf_low = opf_low,
|
||||
.rs2 = rs2.enc(),
|
||||
@ -979,6 +1141,14 @@ pub const Instruction = union(enum) {
|
||||
};
|
||||
}
|
||||
|
||||
pub fn bpcc(cond: ICondition, annul: bool, pt: bool, ccr: CCR, disp: i21) Instruction {
|
||||
return format2c(0b001, .{ .icond = cond }, annul, pt, ccr, disp);
|
||||
}
|
||||
|
||||
pub fn bpr(cond: RCondition, annul: bool, pt: bool, rs1: Register, disp: i18) Instruction {
|
||||
return format2d(0b011, cond, annul, pt, rs1, disp);
|
||||
}
|
||||
|
||||
pub fn jmpl(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
|
||||
return switch (s2) {
|
||||
Register => format3a(0b10, 0b11_1000, rs1, rs2, rd),
|
||||
@ -1027,6 +1197,14 @@ pub const Instruction = union(enum) {
|
||||
};
|
||||
}
|
||||
|
||||
pub fn mulx(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
|
||||
return switch (s2) {
|
||||
Register => format3a(0b10, 0b00_1001, rs1, rs2, rd),
|
||||
i13 => format3b(0b10, 0b00_1001, rs1, rs2, rd),
|
||||
else => unreachable,
|
||||
};
|
||||
}
|
||||
|
||||
pub fn nop() Instruction {
|
||||
return sethi(0, .g0);
|
||||
}
|
||||
@ -1099,11 +1277,19 @@ pub const Instruction = union(enum) {
|
||||
};
|
||||
}
|
||||
|
||||
pub fn trap(comptime s2: type, cond: Condition, ccr: CCR, rs1: Register, rs2: s2) Instruction {
|
||||
pub fn subcc(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
|
||||
return switch (s2) {
|
||||
Register => format3a(0b10, 0b01_0100, rs1, rs2, rd),
|
||||
i13 => format3b(0b10, 0b01_0100, rs1, rs2, rd),
|
||||
else => unreachable,
|
||||
};
|
||||
}
|
||||
|
||||
pub fn trap(comptime s2: type, cond: ICondition, ccr: CCR, rs1: Register, rs2: s2) Instruction {
|
||||
// Tcc instructions abuse the rd field to store the conditionals.
|
||||
return switch (s2) {
|
||||
Register => format4a(0b11_1010, ccr, rs1, rs2, @intToEnum(Register, cond)),
|
||||
u7 => format4e(0b11_1010, ccr, rs1, @intToEnum(Register, cond), rs2),
|
||||
Register => format4a(0b11_1010, ccr, rs1, rs2, @intToEnum(Register, @enumToInt(cond))),
|
||||
u7 => format4e(0b11_1010, ccr, rs1, @intToEnum(Register, @enumToInt(cond)), rs2),
|
||||
else => unreachable,
|
||||
};
|
||||
}
|
||||
@ -1128,11 +1314,11 @@ test "Serialize formats" {
|
||||
.expected = 0b00_00000_100_0000000000000000000000,
|
||||
},
|
||||
.{
|
||||
.inst = Instruction.format2b(6, 3, true, -4),
|
||||
.inst = Instruction.format2b(6, .{ .icond = .lt }, true, -4),
|
||||
.expected = 0b00_1_0011_110_1111111111111111111111,
|
||||
},
|
||||
.{
|
||||
.inst = Instruction.format2c(3, 0, false, true, .xcc, 8),
|
||||
.inst = Instruction.format2c(3, .{ .icond = .nv }, false, true, .xcc, 8),
|
||||
.expected = 0b00_0_0000_011_1_0_1_0000000000000000010,
|
||||
},
|
||||
.{
|
||||
@ -1224,11 +1410,11 @@ test "Serialize formats" {
|
||||
.expected = 0b10_10010_001000_00000_1_1_0_11111111111,
|
||||
},
|
||||
.{
|
||||
.inst = Instruction.format4c(8, 0, .xcc, .g0, .o1),
|
||||
.inst = Instruction.format4c(8, .{ .icond = .nv }, .xcc, .g0, .o1),
|
||||
.expected = 0b10_01001_001000_1_0000_0_1_0_000000_00000,
|
||||
},
|
||||
.{
|
||||
.inst = Instruction.format4d(8, 0, .xcc, 0, .l2),
|
||||
.inst = Instruction.format4d(8, .{ .icond = .nv }, .xcc, 0, .l2),
|
||||
.expected = 0b10_10010_001000_1_0000_1_1_0_00000000000,
|
||||
},
|
||||
.{
|
||||
@ -1240,7 +1426,7 @@ test "Serialize formats" {
|
||||
.expected = 0b10_10010_001000_00000_0_001_00100_01001,
|
||||
},
|
||||
.{
|
||||
.inst = Instruction.format4g(8, 4, 2, 0, .o1, .l2),
|
||||
.inst = Instruction.format4g(8, 4, 2, .{ .icond = .nv }, .o1, .l2),
|
||||
.expected = 0b10_10010_001000_0_0000_010_000100_01001,
|
||||
},
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user