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x86 backend: don't read bogus safety flag

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Safety is not a global flag that should be enabled or disabled for all
stores - it's lowered by the frontend directly into AIR instruction
semantics. The flag for this is communicated via the `store` vs
`store_safe` AIR instructions, and whether to write 0xaa bytes or not
should be decided in `airStore` and passed down via function parameters.

This commit is a step backwards since it removes functionality but it
aims our feet towards a better mountain to climb.
This commit is contained in:
Andrew Kelley 2023-09-18 21:24:50 -07:00
parent f91ff9a746
commit 3e79315d19
3 changed files with 6 additions and 16 deletions
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18
src/arch/x86_64/CodeGen.zig
View File

@ -1934,7 +1934,7 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
.ptr_elem_ptr => try self.airPtrElemPtr(inst),
.inferred_alloc, .inferred_alloc_comptime => unreachable,
.unreach => if (self.wantSafety()) try self.airTrap() else self.finishAirBookkeeping(),
.unreach => self.finishAirBookkeeping(),
.optional_payload => try self.airOptionalPayload(inst),
.optional_payload_ptr => try self.airOptionalPayloadPtr(inst),
@ -9813,8 +9813,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
.register_overflow,
.reserved_frame,
=> unreachable,
.undef => if (self.wantSafety())
try self.genSetReg(dst_reg.to64(), Type.usize, .{ .immediate = 0xaaaaaaaaaaaaaaaa }),
.undef => {},
.eflags => |cc| try self.asmSetccRegister(dst_reg.to8(), cc),
.immediate => |imm| {
if (imm == 0) {
@ -10098,8 +10097,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
};
switch (src_mcv) {
.none, .unreach, .dead, .reserved_frame => unreachable,
.undef => if (self.wantSafety())
try self.genInlineMemset(dst_ptr_mcv, .{ .immediate = 0xaa }, .{ .immediate = abi_size }),
.undef => {},
.immediate => |imm| switch (abi_size) {
1, 2, 4 => {
const immediate = if (ty.isSignedInt(mod))
@ -12016,16 +12014,6 @@ fn resolveCallingConventionValues(
return result;
}
/// TODO support scope overrides. Also note this logic is duplicated with `Module.wantSafety`.
fn wantSafety(self: *Self) bool {
return switch (self.bin_file.options.optimize_mode) {
.Debug => true,
.ReleaseSafe => true,
.ReleaseFast => false,
.ReleaseSmall => false,
};
}
fn fail(self: *Self, comptime format: []const u8, args: anytype) InnerError {
@setCold(true);
assert(self.err_msg == null);

3
test/behavior/cast.zig
View File

@ -334,10 +334,11 @@ test "*const ?[*]const T to [*c]const [*c]const T" {
try expect(b[0][1] == 'k');
}
test "array coersion to undefined at runtime" {
test "array coercion to undefined at runtime" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
@setRuntimeSafety(true);

1
test/behavior/int128.zig
View File

@ -28,6 +28,7 @@ test "undefined 128 bit int" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
@setRuntimeSafety(true);