mirror/zig
1
0
Fork 0
mirror of https://github.com/ziglang/zig.git synced 2025-12-06 14:23:09 +00:00
Code Issues Packages Projects Releases Wiki Activity

std.zig.system.linux: Add detection for some extra RISC-V CPUs

Browse Source
This commit is contained in:
Alex Rønne Petersen 2025-06-30 06:59:06 +02:00
parent fd2d4507c8
commit 3d7fb4f204
No known key found for this signature in database
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/std/zig/system/linux.zig
View File

@ -76,9 +76,11 @@ const RiscvCpuinfoImpl = struct {
const cpu_names = .{
.{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
.{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
.{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
.{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
.{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
.{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
};
fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {