From 316b4bde6a118c0742eee0d45137268a1dc99a26 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Tue, 4 Aug 2020 21:46:49 -0700 Subject: [PATCH] update target CPU features from llvm 10 to 11rc1 --- lib/std/target.zig | 2 +- lib/std/target/aarch64.zig | 208 +++++++++++++++++++++++++++++++++++-- lib/std/target/amdgpu.zig | 143 ++++++++++++++++++------- lib/std/target/arm.zig | 171 ++++++++++++++++++++++++++++++ lib/std/target/avr.zig | 23 +++- lib/std/target/hexagon.zig | 101 ++++++++++++++++++ lib/std/target/mips.zig | 6 ++ lib/std/target/nvptx.zig | 26 +++++ lib/std/target/powerpc.zig | 122 +++++++++++++++++++++- lib/std/target/riscv.zig | 142 ++++++++++++++++++++++--- lib/std/target/systemz.zig | 6 ++ lib/std/target/wasm.zig | 8 ++ lib/std/target/x86.zig | 100 ++++++++++++++++-- 13 files changed, 991 insertions(+), 67 deletions(-) diff --git a/lib/std/target.zig b/lib/std/target.zig index 04a65b45ad..596b968918 100644 --- a/lib/std/target.zig +++ b/lib/std/target.zig @@ -485,7 +485,7 @@ pub const Target = struct { pub const Set = struct { ints: [usize_count]usize, - pub const needed_bit_count = 155; + pub const needed_bit_count = 168; pub const byte_count = (needed_bit_count + 7) / 8; pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize); pub const Index = std.math.Log2Int(std.meta.Int(false, usize_count * @bitSizeOf(usize))); diff --git a/lib/std/target/aarch64.zig b/lib/std/target/aarch64.zig index 9af95dfada..8c978cb650 100644 --- a/lib/std/target/aarch64.zig +++ b/lib/std/target/aarch64.zig @@ -3,6 +3,7 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { + a34, a65, a76, aes, @@ -10,6 +11,7 @@ pub const Feature = enum { alternate_sextload_cvt_f32_pattern, altnzcv, am, + amvs, apple_a10, apple_a11, apple_a12, @@ -18,6 +20,7 @@ pub const Feature = enum { arith_bcc_fusion, arith_cbz_fusion, balance_fp_ops, + bf16, bti, call_saved_x10, call_saved_x11, @@ -38,9 +41,13 @@ pub const Feature = enum { disable_latency_sched_heuristic, dit, dotprod, + ecv, ete, exynos_cheap_as_move, exynosm4, + f32mm, + f64mm, + fgt, fmi, force_32bit_jump_tables, fp_armv8, @@ -53,6 +60,9 @@ pub const Feature = enum { fuse_crypto_eor, fuse_csel, fuse_literals, + harden_sls_blr, + harden_sls_retbr, + i8mm, jsconv, lor, lse, @@ -96,6 +106,7 @@ pub const Feature = enum { reserve_x27, reserve_x28, reserve_x3, + reserve_x30, reserve_x4, reserve_x5, reserve_x6, @@ -129,6 +140,7 @@ pub const Feature = enum { trbe, uaops, use_aa, + use_experimental_zeroing_pseudos, use_postra_scheduler, use_reciprocal_square_root, v8a, @@ -137,6 +149,7 @@ pub const Feature = enum { v8_3a, v8_4a, v8_5a, + v8_6a, vh, zcm, zcz, @@ -152,6 +165,16 @@ pub const all_features = blk: { const len = @typeInfo(Feature).Enum.fields.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; + result[@enumToInt(Feature.a34)] = .{ + .llvm_name = "a35", + .description = "Cortex-A34 ARM processors", + .dependencies = featureSet(&[_]Feature{ + .crc, + .crypto, + .perfmon, + .v8a, + }), + }; result[@enumToInt(Feature.a65)] = .{ .llvm_name = "a65", .description = "Cortex-A65 ARM processors", @@ -206,6 +229,13 @@ pub const all_features = blk: { .description = "Enable v8.4-A Activity Monitors extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.amvs)] = .{ + .llvm_name = "amvs", + .description = "Enable v8.6-A Activity Monitors Virtualization support", + .dependencies = featureSet(&[_]Feature{ + .am, + }), + }; result[@enumToInt(Feature.apple_a10)] = .{ .llvm_name = "apple-a10", .description = "Apple A10", @@ -325,6 +355,11 @@ pub const all_features = blk: { .description = "balance mix of odd and even D-registers for fp multiply(-accumulate) ops", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.bf16)] = .{ + .llvm_name = "bf16", + .description = "Enable BFloat16 Extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.bti)] = .{ .llvm_name = "bti", .description = "Enable Branch Target Identification", @@ -431,6 +466,11 @@ pub const all_features = blk: { .description = "Enable dot product support", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.ecv)] = .{ + .llvm_name = "ecv", + .description = "Enable enhanced counter virtualization extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.ete)] = .{ .llvm_name = "ete", .description = "Enable Embedded Trace Extension", @@ -468,6 +508,25 @@ pub const all_features = blk: { .zcz, }), }; + result[@enumToInt(Feature.f32mm)] = .{ + .llvm_name = "f32mm", + .description = "Enable Matrix Multiply FP32 Extension", + .dependencies = featureSet(&[_]Feature{ + .sve, + }), + }; + result[@enumToInt(Feature.f64mm)] = .{ + .llvm_name = "f64mm", + .description = "Enable Matrix Multiply FP64 Extension", + .dependencies = featureSet(&[_]Feature{ + .sve, + }), + }; + result[@enumToInt(Feature.fgt)] = .{ + .llvm_name = "fgt", + .description = "Enable fine grained virtualization traps extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.fmi)] = .{ .llvm_name = "fmi", .description = "Enable v8.4-A Flag Manipulation Instructions", @@ -532,9 +591,24 @@ pub const all_features = blk: { .description = "CPU fuses literal generation operations", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.harden_sls_blr)] = .{ + .llvm_name = "harden-sls-blr", + .description = "Harden against straight line speculation across BLR instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.harden_sls_retbr)] = .{ + .llvm_name = "harden-sls-retbr", + .description = "Harden against straight line speculation across RET and BR instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.i8mm)] = .{ + .llvm_name = "i8mm", + .description = "Enable Matrix Multiply Int8 Extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.jsconv)] = .{ .llvm_name = "jsconv", - .description = "Enable v8.3-A JavaScript FP conversion enchancement", + .description = "Enable v8.3-A JavaScript FP conversion instructions", .dependencies = featureSet(&[_]Feature{ .fp_armv8, }), @@ -607,12 +681,12 @@ pub const all_features = blk: { }; result[@enumToInt(Feature.nv)] = .{ .llvm_name = "nv", - .description = "Enable v8.4-A Nested Virtualization Enchancement", + .description = "Enable v8.4-A Nested Virtualization extension", .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.pa)] = .{ .llvm_name = "pa", - .description = "Enable v8.3-A Pointer Authentication enchancement", + .description = "Enable v8.3-A Pointer Authentication extension", .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.pan)] = .{ @@ -776,6 +850,11 @@ pub const all_features = blk: { .description = "Reserve X3, making it unavailable as a GPR", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.reserve_x30)] = .{ + .llvm_name = "reserve-x30", + .description = "Reserve X30, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.reserve_x4)] = .{ .llvm_name = "reserve-x4", .description = "Reserve X4, making it unavailable as a GPR", @@ -961,6 +1040,11 @@ pub const all_features = blk: { .description = "Use alias analysis during codegen", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.use_experimental_zeroing_pseudos)] = .{ + .llvm_name = "use-experimental-zeroing-pseudos", + .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.use_postra_scheduler)] = .{ .llvm_name = "use-postra-scheduler", .description = "Schedule again after register allocation", @@ -1049,6 +1133,18 @@ pub const all_features = blk: { .v8_4a, }), }; + result[@enumToInt(Feature.v8_6a)] = .{ + .llvm_name = "v8.6a", + .description = "Support ARM v8.6a instructions", + .dependencies = featureSet(&[_]Feature{ + .amvs, + .bf16, + .ecv, + .fgt, + .i8mm, + .v8_5a, + }), + }; result[@enumToInt(Feature.vh)] = .{ .llvm_name = "vh", .description = "Enables ARM v8.1 Virtual Host extension", @@ -1091,6 +1187,21 @@ pub const all_features = blk: { }; pub const cpu = struct { + pub const a64fx = CpuModel{ + .name = "a64fx", + .llvm_name = "a64fx", + .features = featureSet(&[_]Feature{ + .complxnum, + .fp_armv8, + .fullfp16, + .neon, + .perfmon, + .sha2, + .sve, + .use_postra_scheduler, + .v8_2a, + }), + }; pub const apple_a10 = CpuModel{ .name = "apple_a10", .llvm_name = "apple-a10", @@ -1161,14 +1272,28 @@ pub const cpu = struct { .apple_a12, }), }; + pub const carmel = CpuModel{ + .name = "carmel", + .llvm_name = "carmel", + .features = featureSet(&[_]Feature{ + .crypto, + .fullfp16, + .neon, + .v8_2a, + }), + }; + pub const cortex_a34 = CpuModel{ + .name = "cortex_a34", + .llvm_name = "cortex-a34", + .features = featureSet(&[_]Feature{ + .a34, + }), + }; pub const cortex_a35 = CpuModel{ .name = "cortex_a35", .llvm_name = "cortex-a35", .features = featureSet(&[_]Feature{ - .crc, - .crypto, - .perfmon, - .v8a, + .a34, }), }; pub const cortex_a53 = CpuModel{ @@ -1278,6 +1403,54 @@ pub const cpu = struct { .a76, }), }; + pub const cortex_a77 = CpuModel{ + .name = "cortex_a77", + .llvm_name = "cortex-a77", + .features = featureSet(&[_]Feature{ + .crypto, + .dotprod, + .fp_armv8, + .fullfp16, + .neon, + .rcpc, + .v8_2a, + }), + }; + pub const cortex_a78 = CpuModel{ + .name = "cortex_a78", + .llvm_name = "cortex-a78", + .features = featureSet(&[_]Feature{ + .crypto, + .dotprod, + .fp_armv8, + .fullfp16, + .fuse_aes, + .neon, + .perfmon, + .rcpc, + .spe, + .ssbs, + .use_postra_scheduler, + .v8_2a, + }), + }; + pub const cortex_x1 = CpuModel{ + .name = "cortex_x1", + .llvm_name = "cortex-x1", + .features = featureSet(&[_]Feature{ + .crypto, + .dotprod, + .fp_armv8, + .fullfp16, + .fuse_aes, + .neon, + .perfmon, + .rcpc, + .spe, + .use_postra_scheduler, + .v8_2a, + }), + }; pub const cyclone = CpuModel{ .name = "cyclone", .llvm_name = "cyclone", @@ -1452,6 +1625,27 @@ pub const cpu = struct { .v8_1a, }), }; + pub const thunderx3t110 = CpuModel{ + .name = "thunderx3t110", + .llvm_name = "thunderx3t110", + .features = featureSet(&[_]Feature{ + .aggressive_fma, + .arith_bcc_fusion, + .balance_fp_ops, + .crc, + .crypto, + .fp_armv8, + .lse, + .neon, + .pa, + .perfmon, + .predictable_select_expensive, + .strict_align, + .use_aa, + .use_postra_scheduler, + .v8_3a, + }), + }; pub const thunderxt81 = CpuModel{ .name = "thunderxt81", .llvm_name = "thunderxt81", diff --git a/lib/std/target/amdgpu.zig b/lib/std/target/amdgpu.zig index 4b3f83bbc3..cd1bb23aaf 100644 --- a/lib/std/target/amdgpu.zig +++ b/lib/std/target/amdgpu.zig @@ -5,6 +5,7 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { @"16_bit_insts", DumpCode, + a16, add_no_carry_insts, aperture_regs, atomic_fadd_insts, @@ -21,9 +22,11 @@ pub const Feature = enum { dot6_insts, dpp, dpp8, + ds_src2_insts, dumpcode, enable_ds128, enable_prt_strict_null, + fast_denormal_f32, fast_fmaf, flat_address_space, flat_for_global, @@ -33,15 +36,14 @@ pub const Feature = enum { flat_segment_offset_bug, fma_mix_insts, fmaf, - fp_exceptions, - fp16_denormals, - fp32_denormals, fp64, - fp64_denormals, - fp64_fp16_denormals, + g16, gcn3_encoding, + get_wave_id_inst, gfx10, + gfx10_3_insts, gfx10_insts, + gfx10_b_encoding, gfx7_gfx8_gfx9_insts, gfx8_insts, gfx9, @@ -58,6 +60,7 @@ pub const Feature = enum { localmemorysize0, localmemorysize32768, localmemorysize65536, + mad_mac_f32_insts, mad_mix_insts, mai_insts, max_private_element_size_16, @@ -78,6 +81,7 @@ pub const Feature = enum { r128_a16, register_banking, s_memrealtime, + s_memtime_inst, scalar_atomics, scalar_flat_scratch_insts, scalar_stores, @@ -129,6 +133,11 @@ pub const all_features = blk: { .description = "Dump MachineInstrs in the CodeEmitter", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.a16)] = .{ + .llvm_name = "a16", + .description = "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.add_no_carry_insts)] = .{ .llvm_name = "add-no-carry-insts", .description = "Have VALU add/sub instructions without carry out", @@ -142,7 +151,9 @@ pub const all_features = blk: { result[@enumToInt(Feature.atomic_fadd_insts)] = .{ .llvm_name = "atomic-fadd-insts", .description = "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .flat_global_insts, + }), }; result[@enumToInt(Feature.auto_waitcnt_before_barrier)] = .{ .llvm_name = "auto-waitcnt-before-barrier", @@ -209,6 +220,11 @@ pub const all_features = blk: { .description = "Support DPP8 (Data Parallel Primitives) extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.ds_src2_insts)] = .{ + .llvm_name = "ds-src2-insts", + .description = "Has ds_*_src2 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.dumpcode)] = .{ .llvm_name = "dumpcode", .description = "Dump MachineInstrs in the CodeEmitter", @@ -224,6 +240,11 @@ pub const all_features = blk: { .description = "Enable zeroing of result registers for sparse texture fetches", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.fast_denormal_f32)] = .{ + .llvm_name = "fast-denormal-f32", + .description = "Enabling denormals does not cause f32 instructions to run at f64 rates", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.fast_fmaf)] = .{ .llvm_name = "fast-fmaf", .description = "Assuming f32 fma is at least as fast as mul + add", @@ -269,58 +290,38 @@ pub const all_features = blk: { .description = "Enable single precision FMA (not as fast as mul+add, but fused)", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.fp_exceptions)] = .{ - .llvm_name = "fp-exceptions", - .description = "Enable floating point exceptions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@enumToInt(Feature.fp16_denormals)] = .{ - .llvm_name = "fp16-denormals", - .description = "Enable half precision denormal handling", - .dependencies = featureSet(&[_]Feature{ - .fp64_fp16_denormals, - }), - }; - result[@enumToInt(Feature.fp32_denormals)] = .{ - .llvm_name = "fp32-denormals", - .description = "Enable single precision denormal handling", - .dependencies = featureSet(&[_]Feature{}), - }; result[@enumToInt(Feature.fp64)] = .{ .llvm_name = "fp64", .description = "Enable double precision operations", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.fp64_denormals)] = .{ - .llvm_name = "fp64-denormals", - .description = "Enable double and half precision denormal handling", - .dependencies = featureSet(&[_]Feature{ - .fp64, - .fp64_fp16_denormals, - }), - }; - result[@enumToInt(Feature.fp64_fp16_denormals)] = .{ - .llvm_name = "fp64-fp16-denormals", - .description = "Enable double and half precision denormal handling", - .dependencies = featureSet(&[_]Feature{ - .fp64, - }), + result[@enumToInt(Feature.g16)] = .{ + .llvm_name = "g16", + .description = "Support G16 for 16-bit gradient image operands", + .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.gcn3_encoding)] = .{ .llvm_name = "gcn3-encoding", .description = "Encoding format for VI", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.get_wave_id_inst)] = .{ + .llvm_name = "get-wave-id-inst", + .description = "Has s_get_waveid_in_workgroup instruction", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.gfx10)] = .{ .llvm_name = "gfx10", .description = "GFX10 GPU generation", .dependencies = featureSet(&[_]Feature{ .@"16_bit_insts", + .a16, .add_no_carry_insts, .aperture_regs, .ci_insts, .dpp, .dpp8, + .fast_denormal_f32, .fast_fmaf, .flat_address_space, .flat_global_insts, @@ -328,6 +329,7 @@ pub const all_features = blk: { .flat_scratch_insts, .fma_mix_insts, .fp64, + .g16, .gfx10_insts, .gfx8_insts, .gfx9_insts, @@ -351,11 +353,21 @@ pub const all_features = blk: { .vscnt, }), }; + result[@enumToInt(Feature.gfx10_3_insts)] = .{ + .llvm_name = "gfx10-3-insts", + .description = "Additional instructions for GFX10.3", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.gfx10_insts)] = .{ .llvm_name = "gfx10-insts", .description = "Additional instructions for GFX10+", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.gfx10_b_encoding)] = .{ + .llvm_name = "gfx10_b-encoding", + .description = "Encoding format GFX10_B", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.gfx7_gfx8_gfx9_insts)] = .{ .llvm_name = "gfx7-gfx8-gfx9-insts", .description = "Instructions shared in GFX7, GFX8, GFX9", @@ -375,6 +387,8 @@ pub const all_features = blk: { .aperture_regs, .ci_insts, .dpp, + .ds_src2_insts, + .fast_denormal_f32, .fast_fmaf, .flat_address_space, .flat_global_insts, @@ -388,8 +402,10 @@ pub const all_features = blk: { .int_clamp_insts, .inv_2pi_inline_imm, .localmemorysize65536, + .mad_mac_f32_insts, .r128_a16, .s_memrealtime, + .s_memtime_inst, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, @@ -467,6 +483,11 @@ pub const all_features = blk: { .description = "The size of local memory in bytes", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.mad_mac_f32_insts)] = .{ + .llvm_name = "mad-mac-f32-insts", + .description = "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.mad_mix_insts)] = .{ .llvm_name = "mad-mix-insts", .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", @@ -554,7 +575,7 @@ pub const all_features = blk: { }; result[@enumToInt(Feature.r128_a16)] = .{ .llvm_name = "r128-a16", - .description = "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9", + .description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128", .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.register_banking)] = .{ @@ -567,6 +588,11 @@ pub const all_features = blk: { .description = "Has s_memrealtime instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.s_memtime_inst)] = .{ + .llvm_name = "s-memtime-inst", + .description = "Has s_memtime instruction", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.scalar_atomics)] = .{ .llvm_name = "scalar-atomics", .description = "Has atomic scalar memory instructions", @@ -617,13 +643,16 @@ pub const all_features = blk: { .description = "SEA_ISLANDS GPU generation", .dependencies = featureSet(&[_]Feature{ .ci_insts, + .ds_src2_insts, .flat_address_space, .fp64, .gfx7_gfx8_gfx9_insts, .localmemorysize65536, + .mad_mac_f32_insts, .mimg_r128, .movrel, .no_sram_ecc_support, + .s_memtime_inst, .trig_reduced_range, .wavefrontsize64, }), @@ -647,13 +676,16 @@ pub const all_features = blk: { .llvm_name = "southern-islands", .description = "SOUTHERN_ISLANDS GPU generation", .dependencies = featureSet(&[_]Feature{ + .ds_src2_insts, .fp64, .ldsbankcount32, .localmemorysize32768, + .mad_mac_f32_insts, .mimg_r128, .movrel, .no_sram_ecc_support, .no_xnack_support, + .s_memtime_inst, .trig_reduced_range, .wavefrontsize64, }), @@ -720,6 +752,8 @@ pub const all_features = blk: { .@"16_bit_insts", .ci_insts, .dpp, + .ds_src2_insts, + .fast_denormal_f32, .flat_address_space, .fp64, .gcn3_encoding, @@ -728,10 +762,12 @@ pub const all_features = blk: { .int_clamp_insts, .inv_2pi_inline_imm, .localmemorysize65536, + .mad_mac_f32_insts, .mimg_r128, .movrel, .no_sram_ecc_support, .s_memrealtime, + .s_memtime_inst, .scalar_stores, .sdwa, .sdwa_mav, @@ -840,16 +876,20 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .code_object_v3, .dl_insts, + .ds_src2_insts, .flat_segment_offset_bug, + .get_wave_id_inst, .gfx10, .inst_fwd_prefetch_bug, .lds_branch_vmem_war_hazard, .lds_misaligned_bug, .ldsbankcount32, + .mad_mac_f32_insts, .no_xnack_support, .nsa_encoding, .nsa_to_vmem_bug, .offset_3f_bug, + .s_memtime_inst, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, @@ -870,15 +910,19 @@ pub const cpu = struct { .dot2_insts, .dot5_insts, .dot6_insts, + .ds_src2_insts, .flat_segment_offset_bug, + .get_wave_id_inst, .gfx10, .inst_fwd_prefetch_bug, .lds_branch_vmem_war_hazard, .ldsbankcount32, + .mad_mac_f32_insts, .no_xnack_support, .nsa_encoding, .nsa_to_vmem_bug, .offset_3f_bug, + .s_memtime_inst, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, @@ -899,16 +943,20 @@ pub const cpu = struct { .dot2_insts, .dot5_insts, .dot6_insts, + .ds_src2_insts, .flat_segment_offset_bug, + .get_wave_id_inst, .gfx10, .inst_fwd_prefetch_bug, .lds_branch_vmem_war_hazard, .lds_misaligned_bug, .ldsbankcount32, + .mad_mac_f32_insts, .no_xnack_support, .nsa_encoding, .nsa_to_vmem_bug, .offset_3f_bug, + .s_memtime_inst, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, @@ -919,6 +967,25 @@ pub const cpu = struct { .wavefrontsize32, }), }; + pub const gfx1030 = CpuModel{ + .name = "gfx1030", + .llvm_name = "gfx1030", + .features = featureSet(&[_]Feature{ + .code_object_v3, + .dl_insts, + .dot1_insts, + .dot2_insts, + .dot5_insts, + .dot6_insts, + .gfx10, + .gfx10_3_insts, + .gfx10_b_encoding, + .ldsbankcount32, + .no_xnack_support, + .nsa_encoding, + .wavefrontsize32, + }), + }; pub const gfx600 = CpuModel{ .name = "gfx600", .llvm_name = "gfx600", diff --git a/lib/std/target/arm.zig b/lib/std/target/arm.zig index 90b060c03f..ac11ef3aa7 100644 --- a/lib/std/target/arm.zig +++ b/lib/std/target/arm.zig @@ -11,6 +11,16 @@ pub const Feature = enum { aes, avoid_movs_shop, avoid_partial_cpsr, + bf16, + cde, + cdecp0, + cdecp1, + cdecp2, + cdecp3, + cdecp4, + cdecp5, + cdecp6, + cdecp7, cheap_predicable_cpsr, crc, crypto, @@ -53,11 +63,13 @@ pub const Feature = enum { has_v8_3a, has_v8_4a, has_v8_5a, + has_v8_6a, has_v8, has_v8m, has_v8m_main, hwdiv, hwdiv_arm, + i8mm, iwmmxt, iwmmxt2, lob, @@ -141,6 +153,7 @@ pub const Feature = enum { v8_3a, v8_4a, v8_5a, + v8_6a, vfp2, vfp2sp, vfp3, @@ -209,6 +222,76 @@ pub const all_features = blk: { .description = "Avoid CPSR partial update for OOO execution", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.bf16)] = .{ + .llvm_name = "bf16", + .description = "Enable support for BFloat16 instructions", + .dependencies = featureSet(&[_]Feature{ + .neon, + }), + }; + result[@enumToInt(Feature.cde)] = .{ + .llvm_name = "cde", + .description = "Support CDE instructions", + .dependencies = featureSet(&[_]Feature{ + .v8m_main, + }), + }; + result[@enumToInt(Feature.cdecp0)] = .{ + .llvm_name = "cdecp0", + .description = "Coprocessor 0 ISA is CDEv1", + .dependencies = featureSet(&[_]Feature{ + .cde, + }), + }; + result[@enumToInt(Feature.cdecp1)] = .{ + .llvm_name = "cdecp1", + .description = "Coprocessor 1 ISA is CDEv1", + .dependencies = featureSet(&[_]Feature{ + .cde, + }), + }; + result[@enumToInt(Feature.cdecp2)] = .{ + .llvm_name = "cdecp2", + .description = "Coprocessor 2 ISA is CDEv1", + .dependencies = featureSet(&[_]Feature{ + .cde, + }), + }; + result[@enumToInt(Feature.cdecp3)] = .{ + .llvm_name = "cdecp3", + .description = "Coprocessor 3 ISA is CDEv1", + .dependencies = featureSet(&[_]Feature{ + .cde, + }), + }; + result[@enumToInt(Feature.cdecp4)] = .{ + .llvm_name = "cdecp4", + .description = "Coprocessor 4 ISA is CDEv1", + .dependencies = featureSet(&[_]Feature{ + .cde, + }), + }; + result[@enumToInt(Feature.cdecp5)] = .{ + .llvm_name = "cdecp5", + .description = "Coprocessor 5 ISA is CDEv1", + .dependencies = featureSet(&[_]Feature{ + .cde, + }), + }; + result[@enumToInt(Feature.cdecp6)] = .{ + .llvm_name = "cdecp6", + .description = "Coprocessor 6 ISA is CDEv1", + .dependencies = featureSet(&[_]Feature{ + .cde, + }), + }; + result[@enumToInt(Feature.cdecp7)] = .{ + .llvm_name = "cdecp7", + .description = "Coprocessor 7 ISA is CDEv1", + .dependencies = featureSet(&[_]Feature{ + .cde, + }), + }; result[@enumToInt(Feature.cheap_predicable_cpsr)] = .{ .llvm_name = "cheap-predicable-cpsr", .description = "Disable +1 predication cost for instructions updating CPSR", @@ -508,6 +591,15 @@ pub const all_features = blk: { .has_v8_4a, }), }; + result[@enumToInt(Feature.has_v8_6a)] = .{ + .llvm_name = "v8.6a", + .description = "Support ARM v8.6a instructions", + .dependencies = featureSet(&[_]Feature{ + .bf16, + .i8mm, + .has_v8_5a, + }), + }; result[@enumToInt(Feature.has_v8m)] = .{ .llvm_name = "v8m", .description = "Support ARM v8M Baseline instructions", @@ -532,6 +624,13 @@ pub const all_features = blk: { .description = "Enable divide instructions in ARM mode", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.i8mm)] = .{ + .llvm_name = "i8mm", + .description = "Enable Matrix Multiply Int8 Extension", + .dependencies = featureSet(&[_]Feature{ + .neon, + }), + }; result[@enumToInt(Feature.iwmmxt)] = .{ .llvm_name = "iwmmxt", .description = "ARMv5te architecture", @@ -1177,6 +1276,25 @@ pub const all_features = blk: { .virtualization, }), }; + result[@enumToInt(Feature.v8_6a)] = .{ + .llvm_name = "armv8.6-a", + .description = "ARMv86a architecture", + .dependencies = featureSet(&[_]Feature{ + .aclass, + .crc, + .crypto, + .db, + .dotprod, + .dsp, + .fp_armv8, + .mp, + .neon, + .ras, + .trustzone, + .has_v8_6a, + .virtualization, + }), + }; result[@enumToInt(Feature.vfp2)] = .{ .llvm_name = "vfp2", .description = "Enable VFP2 instructions", @@ -1722,6 +1840,32 @@ pub const cpu = struct { .hwdiv_arm, }), }; + pub const cortex_a77 = CpuModel{ + .name = "cortex_a77", + .llvm_name = "cortex-a77", + .features = featureSet(&[_]Feature{ + .v8_2a, + .crc, + .crypto, + .dotprod, + .fullfp16, + .hwdiv, + .hwdiv_arm, + }), + }; + pub const cortex_a78 = CpuModel{ + .name = "cortex_a78", + .llvm_name = "cortex-a78", + .features = featureSet(&[_]Feature{ + .v8_2a, + .crc, + .crypto, + .dotprod, + .fullfp16, + .hwdiv, + .hwdiv_arm, + }), + }; pub const cortex_a8 = CpuModel{ .name = "cortex_a8", .llvm_name = "cortex-a8", @@ -1837,6 +1981,20 @@ pub const cpu = struct { .vfp4d16sp, }), }; + pub const cortex_m55 = CpuModel{ + .name = "cortex_m55", + .llvm_name = "cortex-m55", + .features = featureSet(&[_]Feature{ + .v8_1m_main, + .dsp, + .fp_armv8d16, + .loop_align, + .mve_fp, + .no_branch_predictor, + .slowfpvmlx, + .use_misched, + }), + }; pub const cortex_m7 = CpuModel{ .name = "cortex_m7", .llvm_name = "cortex-m7", @@ -1924,6 +2082,19 @@ pub const cpu = struct { .vfp3d16, }), }; + pub const cortex_x1 = CpuModel{ + .name = "cortex_x1", + .llvm_name = "cortex-x1", + .features = featureSet(&[_]Feature{ + .v8_2a, + .crc, + .crypto, + .dotprod, + .fullfp16, + .hwdiv, + .hwdiv_arm, + }), + }; pub const cyclone = CpuModel{ .name = "cyclone", .llvm_name = "cyclone", diff --git a/lib/std/target/avr.zig b/lib/std/target/avr.zig index af4f5ba5be..727aec6db3 100644 --- a/lib/std/target/avr.zig +++ b/lib/std/target/avr.zig @@ -25,6 +25,7 @@ pub const Feature = enum { jmpcall, lpm, lpmx, + memmappedregs, movw, mul, rmw, @@ -60,6 +61,7 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .avr0, .lpm, + .memmappedregs, }), }; result[@enumToInt(Feature.avr2)] = .{ @@ -156,6 +158,7 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .avr0, .@"break", + .memmappedregs, .sram, .tinyencoding, }), @@ -205,6 +208,11 @@ pub const all_features = blk: { .description = "The device supports the `LPM Rd, Z[+]` instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.memmappedregs)] = .{ + .llvm_name = "memmappedregs", + .description = "The device has CPU registers mapped in data address space", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.movw)] = .{ .llvm_name = "movw", .description = "The device supports the 16-bit MOVW instruction", @@ -239,6 +247,7 @@ pub const all_features = blk: { .jmpcall, .lpm, .lpmx, + .memmappedregs, .movw, .mul, .rmw, @@ -271,10 +280,22 @@ pub const all_features = blk: { .llvm_name = "xmega", .description = "The device is a part of the xmega family", .dependencies = featureSet(&[_]Feature{ - .avr51, + .addsubiw, + .avr0, + .@"break", .des, .eijmpcall, + .elpm, + .elpmx, + .ijmpcall, + .jmpcall, + .lpm, + .lpmx, + .movw, + .mul, + .spm, .spmx, + .sram, }), }; result[@enumToInt(Feature.xmegau)] = .{ diff --git a/lib/std/target/hexagon.zig b/lib/std/target/hexagon.zig index f429099d88..bc1c744cd1 100644 --- a/lib/std/target/hexagon.zig +++ b/lib/std/target/hexagon.zig @@ -3,6 +3,8 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { + audio, + compound, duplex, hvx, hvx_length128b, @@ -11,6 +13,7 @@ pub const Feature = enum { hvxv62, hvxv65, hvxv66, + hvxv67, long_calls, mem_noshuf, memops, @@ -18,14 +21,18 @@ pub const Feature = enum { nvj, nvs, packets, + prev65, reserved_r19, small_data, + tinycore, + unsafe_fp, v5, v55, v60, v62, v65, v66, + v67, zreg, }; @@ -35,6 +42,16 @@ pub const all_features = blk: { const len = @typeInfo(Feature).Enum.fields.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; + result[@enumToInt(Feature.audio)] = .{ + .llvm_name = "audio", + .description = "Hexagon Audio extension instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.compound)] = .{ + .llvm_name = "compound", + .description = "Use compound instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.duplex)] = .{ .llvm_name = "duplex", .description = "Enable generation of duplex instruction", @@ -94,6 +111,16 @@ pub const all_features = blk: { .zreg, }), }; + result[@enumToInt(Feature.hvxv67)] = .{ + .llvm_name = "hvxv67", + .description = "Hexagon HVX instructions", + .dependencies = featureSet(&[_]Feature{ + .hvxv60, + .hvxv62, + .hvxv65, + .hvxv66, + }), + }; result[@enumToInt(Feature.long_calls)] = .{ .llvm_name = "long-calls", .description = "Use constant-extended calls", @@ -133,6 +160,11 @@ pub const all_features = blk: { .description = "Support for instruction packets", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.prev65)] = .{ + .llvm_name = "prev65", + .description = "Support features deprecated in v65", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.reserved_r19)] = .{ .llvm_name = "reserved-r19", .description = "Reserve register R19", @@ -143,6 +175,16 @@ pub const all_features = blk: { .description = "Allow GP-relative addressing of global variables", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.tinycore)] = .{ + .llvm_name = "tinycore", + .description = "Hexagon Tiny Core", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.unsafe_fp)] = .{ + .llvm_name = "unsafe-fp", + .description = "Use unsafe FP math", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.v5)] = .{ .llvm_name = "v5", .description = "Enable Hexagon V5 architecture", @@ -173,6 +215,11 @@ pub const all_features = blk: { .description = "Enable Hexagon V66 architecture", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.v67)] = .{ + .llvm_name = "v67", + .description = "Enable Hexagon V67 architecture", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.zreg)] = .{ .llvm_name = "zreg", .description = "Hexagon ZReg extension instructions", @@ -191,11 +238,13 @@ pub const cpu = struct { .name = "generic", .llvm_name = "generic", .features = featureSet(&[_]Feature{ + .compound, .duplex, .memops, .nvj, .nvs, .packets, + .prev65, .small_data, .v5, .v55, @@ -206,11 +255,13 @@ pub const cpu = struct { .name = "hexagonv5", .llvm_name = "hexagonv5", .features = featureSet(&[_]Feature{ + .compound, .duplex, .memops, .nvj, .nvs, .packets, + .prev65, .small_data, .v5, }), @@ -219,11 +270,13 @@ pub const cpu = struct { .name = "hexagonv55", .llvm_name = "hexagonv55", .features = featureSet(&[_]Feature{ + .compound, .duplex, .memops, .nvj, .nvs, .packets, + .prev65, .small_data, .v5, .v55, @@ -233,11 +286,13 @@ pub const cpu = struct { .name = "hexagonv60", .llvm_name = "hexagonv60", .features = featureSet(&[_]Feature{ + .compound, .duplex, .memops, .nvj, .nvs, .packets, + .prev65, .small_data, .v5, .v55, @@ -248,11 +303,13 @@ pub const cpu = struct { .name = "hexagonv62", .llvm_name = "hexagonv62", .features = featureSet(&[_]Feature{ + .compound, .duplex, .memops, .nvj, .nvs, .packets, + .prev65, .small_data, .v5, .v55, @@ -264,6 +321,7 @@ pub const cpu = struct { .name = "hexagonv65", .llvm_name = "hexagonv65", .features = featureSet(&[_]Feature{ + .compound, .duplex, .mem_noshuf, .memops, @@ -282,6 +340,7 @@ pub const cpu = struct { .name = "hexagonv66", .llvm_name = "hexagonv66", .features = featureSet(&[_]Feature{ + .compound, .duplex, .mem_noshuf, .memops, @@ -297,4 +356,46 @@ pub const cpu = struct { .v66, }), }; + pub const hexagonv67 = CpuModel{ + .name = "hexagonv67", + .llvm_name = "hexagonv67", + .features = featureSet(&[_]Feature{ + .compound, + .duplex, + .mem_noshuf, + .memops, + .nvj, + .nvs, + .packets, + .small_data, + .v5, + .v55, + .v60, + .v62, + .v65, + .v66, + .v67, + }), + }; + pub const hexagonv67t = CpuModel{ + .name = "hexagonv67t", + .llvm_name = "hexagonv67t", + .features = featureSet(&[_]Feature{ + .audio, + .compound, + .mem_noshuf, + .memops, + .nvs, + .packets, + .small_data, + .tinycore, + .v5, + .v55, + .v60, + .v62, + .v65, + .v66, + .v67, + }), + }; }; diff --git a/lib/std/target/mips.zig b/lib/std/target/mips.zig index fc95b2dee8..bc2dc75323 100644 --- a/lib/std/target/mips.zig +++ b/lib/std/target/mips.zig @@ -28,6 +28,7 @@ pub const Feature = enum { mips32r6, mips3_32, mips3_32r2, + mips3d, mips4, mips4_32, mips4_32r2, @@ -222,6 +223,11 @@ pub const all_features = blk: { .description = "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.mips3d)] = .{ + .llvm_name = "mips3d", + .description = "Mips 3D ASE", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.mips4)] = .{ .llvm_name = "mips4", .description = "MIPS IV ISA Support", diff --git a/lib/std/target/nvptx.zig b/lib/std/target/nvptx.zig index d719a6bb71..0caf833726 100644 --- a/lib/std/target/nvptx.zig +++ b/lib/std/target/nvptx.zig @@ -13,6 +13,8 @@ pub const Feature = enum { ptx61, ptx63, ptx64, + ptx65, + ptx70, sm_20, sm_21, sm_30, @@ -28,6 +30,7 @@ pub const Feature = enum { sm_70, sm_72, sm_75, + sm_80, }; pub usingnamespace CpuFeature.feature_set_fns(Feature); @@ -86,6 +89,16 @@ pub const all_features = blk: { .description = "Use PTX version 6.4", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.ptx65)] = .{ + .llvm_name = "ptx65", + .description = "Use PTX version 6.5", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.ptx70)] = .{ + .llvm_name = "ptx70", + .description = "Use PTX version 7.0", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.sm_20)] = .{ .llvm_name = "sm_20", .description = "Target SM 2.0", @@ -161,6 +174,11 @@ pub const all_features = blk: { .description = "Target SM 7.5", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.sm_80)] = .{ + .llvm_name = "sm_80", + .description = "Target SM 8.0", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (result) |*elem, i| { elem.index = i; @@ -286,4 +304,12 @@ pub const cpu = struct { .sm_75, }), }; + pub const sm_80 = CpuModel{ + .name = "sm_80", + .llvm_name = "sm_80", + .features = featureSet(&[_]Feature{ + .ptx70, + .sm_80, + }), + }; }; diff --git a/lib/std/target/powerpc.zig b/lib/std/target/powerpc.zig index ffea7344fc..9410e35a04 100644 --- a/lib/std/target/powerpc.zig +++ b/lib/std/target/powerpc.zig @@ -25,11 +25,15 @@ pub const Feature = enum { frsqrte, frsqrtes, fsqrt, + fuse_addi_load, + fuse_addis_load, + fusion, hard_float, htm, icbt, invariant_function_descriptors, isa_v30_instructions, + isa_v31_instructions, isel, ldbrx, lfiwax, @@ -37,7 +41,9 @@ pub const Feature = enum { mfocrf, msync, partword_atomics, + pcrelative_memops, popcntd, + power10_vector, power8_altivec, power8_vector, power9_altivec, @@ -46,6 +52,8 @@ pub const Feature = enum { ppc_prera_sched, ppc4xx, ppc6xx, + predictable_select_expensive, + prefix_instrs, qpx, recipprec, secure_plt, @@ -201,6 +209,25 @@ pub const all_features = blk: { .fpu, }), }; + result[@enumToInt(Feature.fuse_addi_load)] = .{ + .llvm_name = "fuse-addi-load", + .description = "Power8 Addi-Load fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; + result[@enumToInt(Feature.fuse_addis_load)] = .{ + .llvm_name = "fuse-addis-load", + .description = "Power8 Addis-Load fusion", + .dependencies = featureSet(&[_]Feature{ + .fusion, + }), + }; + result[@enumToInt(Feature.fusion)] = .{ + .llvm_name = "fusion", + .description = "Target supports instruction fusion", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.hard_float)] = .{ .llvm_name = "hard-float", .description = "Enable floating-point instructions", @@ -223,9 +250,16 @@ pub const all_features = blk: { }; result[@enumToInt(Feature.isa_v30_instructions)] = .{ .llvm_name = "isa-v30-instructions", - .description = "Enable instructions added in ISA 3.0.", + .description = "Enable instructions in ISA 3.0.", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.isa_v31_instructions)] = .{ + .llvm_name = "isa-v31-instructions", + .description = "Enable instructions in ISA 3.1.", + .dependencies = featureSet(&[_]Feature{ + .isa_v30_instructions, + }), + }; result[@enumToInt(Feature.isel)] = .{ .llvm_name = "isel", .description = "Enable the isel instruction", @@ -265,11 +299,26 @@ pub const all_features = blk: { .description = "Enable l[bh]arx and st[bh]cx.", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.pcrelative_memops)] = .{ + .llvm_name = "pcrelative-memops", + .description = "Enable PC relative Memory Ops", + .dependencies = featureSet(&[_]Feature{ + .isa_v30_instructions, + }), + }; result[@enumToInt(Feature.popcntd)] = .{ .llvm_name = "popcntd", .description = "Enable the popcnt[dw] instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.power10_vector)] = .{ + .llvm_name = "power10-vector", + .description = "Enable POWER10 vector instructions", + .dependencies = featureSet(&[_]Feature{ + .isa_v31_instructions, + .power9_vector, + }), + }; result[@enumToInt(Feature.power8_altivec)] = .{ .llvm_name = "power8-altivec", .description = "Enable POWER8 Altivec instructions", @@ -322,6 +371,20 @@ pub const all_features = blk: { .description = "Enable PPC 6xx instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.predictable_select_expensive)] = .{ + .llvm_name = "predictable-select-expensive", + .description = "Prefer likely predicted branches over selects", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.prefix_instrs)] = .{ + .llvm_name = "prefix-instrs", + .description = "Enable prefixed instructions", + .dependencies = featureSet(&[_]Feature{ + .isa_v30_instructions, + .power8_vector, + .power9_altivec, + }), + }; result[@enumToInt(Feature.qpx)] = .{ .llvm_name = "qpx", .description = "Enable QPX instructions", @@ -567,6 +630,7 @@ pub const cpu = struct { .booke, .icbt, .isel, + .msync, .spe, }), }; @@ -615,16 +679,21 @@ pub const cpu = struct { .htm, .icbt, .isa_v30_instructions, + .isa_v31_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .partword_atomics, + .pcrelative_memops, .popcntd, + .power10_vector, .power8_altivec, .power8_vector, .power9_altivec, .power9_vector, + .predictable_select_expensive, + .prefix_instrs, .recipprec, .stfiwx, .two_const_nr, @@ -724,6 +793,8 @@ pub const cpu = struct { .frsqrte, .frsqrtes, .fsqrt, + .fuse_addi_load, + .fuse_addis_load, .htm, .icbt, .isel, @@ -734,6 +805,51 @@ pub const cpu = struct { .popcntd, .power8_altivec, .power8_vector, + .predictable_select_expensive, + .recipprec, + .stfiwx, + .two_const_nr, + .vsx, + }), + }; + pub const pwr10 = CpuModel{ + .name = "pwr10", + .llvm_name = "pwr10", + .features = featureSet(&[_]Feature{ + .@"64bit", + .allow_unaligned_fp_access, + .altivec, + .bpermd, + .cmpb, + .crypto, + .direct_move, + .extdiv, + .fcpsgn, + .fpcvt, + .fprnd, + .fre, + .fres, + .frsqrte, + .frsqrtes, + .fsqrt, + .htm, + .icbt, + .isa_v30_instructions, + .isa_v31_instructions, + .isel, + .ldbrx, + .lfiwax, + .mfocrf, + .partword_atomics, + .pcrelative_memops, + .popcntd, + .power10_vector, + .power8_altivec, + .power8_vector, + .power9_altivec, + .power9_vector, + .predictable_select_expensive, + .prefix_instrs, .recipprec, .stfiwx, .two_const_nr, @@ -885,6 +1001,8 @@ pub const cpu = struct { .frsqrte, .frsqrtes, .fsqrt, + .fuse_addi_load, + .fuse_addis_load, .htm, .icbt, .isel, @@ -895,6 +1013,7 @@ pub const cpu = struct { .popcntd, .power8_altivec, .power8_vector, + .predictable_select_expensive, .recipprec, .stfiwx, .two_const_nr, @@ -936,6 +1055,7 @@ pub const cpu = struct { .power9_vector, .ppc_postra_sched, .ppc_prera_sched, + .predictable_select_expensive, .recipprec, .stfiwx, .two_const_nr, diff --git a/lib/std/target/riscv.zig b/lib/std/target/riscv.zig index dbdb107024..187d58ba12 100644 --- a/lib/std/target/riscv.zig +++ b/lib/std/target/riscv.zig @@ -8,8 +8,21 @@ pub const Feature = enum { c, d, e, + experimental_b, + experimental_v, + experimental_zbb, + experimental_zbc, + experimental_zbe, + experimental_zbf, + experimental_zbm, + experimental_zbp, + experimental_zbproposedc, + experimental_zbr, + experimental_zbs, + experimental_zbt, f, m, + no_rvc_hints, relax, reserve_x1, reserve_x10, @@ -42,7 +55,7 @@ pub const Feature = enum { reserve_x7, reserve_x8, reserve_x9, - rvc_hints, + save_restore, }; pub usingnamespace CpuFeature.feature_set_fns(Feature); @@ -78,6 +91,78 @@ pub const all_features = blk: { .description = "Implements RV32E (provides 16 rather than 32 GPRs)", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.experimental_b)] = .{ + .llvm_name = "experimental-b", + .description = "'B' (Bit Manipulation Instructions)", + .dependencies = featureSet(&[_]Feature{ + .experimental_zbb, + .experimental_zbc, + .experimental_zbe, + .experimental_zbf, + .experimental_zbm, + .experimental_zbp, + .experimental_zbr, + .experimental_zbs, + .experimental_zbt, + }), + }; + result[@enumToInt(Feature.experimental_v)] = .{ + .llvm_name = "experimental-v", + .description = "'V' (Vector Instructions)", + .dependencies = featureSet(&[_]Feature{ + .f, + }), + }; + result[@enumToInt(Feature.experimental_zbb)] = .{ + .llvm_name = "experimental-zbb", + .description = "'Zbb' (Base 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbc)] = .{ + .llvm_name = "experimental-zbc", + .description = "'Zbc' (Carry-Less 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbe)] = .{ + .llvm_name = "experimental-zbe", + .description = "'Zbe' (Extract-Deposit 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbf)] = .{ + .llvm_name = "experimental-zbf", + .description = "'Zbf' (Bit-Field 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbm)] = .{ + .llvm_name = "experimental-zbm", + .description = "'Zbm' (Matrix 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbp)] = .{ + .llvm_name = "experimental-zbp", + .description = "'Zbp' (Permutation 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbproposedc)] = .{ + .llvm_name = "experimental-zbproposedc", + .description = "'Zbproposedc' (Proposed Compressed 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbr)] = .{ + .llvm_name = "experimental-zbr", + .description = "'Zbr' (Polynomial Reduction 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbs)] = .{ + .llvm_name = "experimental-zbs", + .description = "'Zbs' (Single-Bit 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.experimental_zbt)] = .{ + .llvm_name = "experimental-zbt", + .description = "'Zbt' (Ternary 'B' Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.f)] = .{ .llvm_name = "f", .description = "'F' (Single-Precision Floating-Point)", @@ -88,6 +173,11 @@ pub const all_features = blk: { .description = "'M' (Integer Multiplication and Division)", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.no_rvc_hints)] = .{ + .llvm_name = "no-rvc-hints", + .description = "Disable RVC Hint Instructions.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.relax)] = .{ .llvm_name = "relax", .description = "Enable Linker relaxation.", @@ -248,9 +338,9 @@ pub const all_features = blk: { .description = "Reserve X9", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.rvc_hints)] = .{ - .llvm_name = "rvc-hints", - .description = "Enable RVC Hint Instructions.", + result[@enumToInt(Feature.save_restore)] = .{ + .llvm_name = "save-restore", + .description = "Enable save/restore.", .dependencies = featureSet(&[_]Feature{}), }; const ti = @typeInfo(Feature); @@ -273,7 +363,6 @@ pub const cpu = struct { .m, }), }; - pub const baseline_rv64 = CpuModel{ .name = "baseline_rv64", .llvm_name = null, @@ -286,20 +375,49 @@ pub const cpu = struct { .m, }), }; - pub const generic_rv32 = CpuModel{ .name = "generic_rv32", - .llvm_name = null, - .features = featureSet(&[_]Feature{ - .rvc_hints, - }), + .llvm_name = "generic-rv32", + .features = featureSet(&[_]Feature{}), }; pub const generic_rv64 = CpuModel{ .name = "generic_rv64", - .llvm_name = null, + .llvm_name = "generic-rv64", .features = featureSet(&[_]Feature{ .@"64bit", - .rvc_hints, + }), + }; + pub const rocket_rv32 = CpuModel{ + .name = "rocket_rv32", + .llvm_name = "rocket-rv32", + .features = featureSet(&[_]Feature{}), + }; + pub const rocket_rv64 = CpuModel{ + .name = "rocket_rv64", + .llvm_name = "rocket-rv64", + .features = featureSet(&[_]Feature{ + .@"64bit", + }), + }; + pub const sifive_e31 = CpuModel{ + .name = "sifive_e31", + .llvm_name = "sifive-e31", + .features = featureSet(&[_]Feature{ + .a, + .c, + .m, + }), + }; + pub const sifive_u54 = CpuModel{ + .name = "sifive_u54", + .llvm_name = "sifive-u54", + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .f, + .m, }), }; }; diff --git a/lib/std/target/systemz.zig b/lib/std/target/systemz.zig index f065a8b169..5c4d9dc127 100644 --- a/lib/std/target/systemz.zig +++ b/lib/std/target/systemz.zig @@ -32,6 +32,7 @@ pub const Feature = enum { population_count, processor_assist, reset_reference_bits_multiple, + soft_float, transactional_execution, vector, vector_enhancements_1, @@ -191,6 +192,11 @@ pub const all_features = blk: { .description = "Assume that the reset-reference-bits-multiple facility is installed", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.soft_float)] = .{ + .llvm_name = "soft-float", + .description = "Use software emulation for floating point", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.transactional_execution)] = .{ .llvm_name = "transactional-execution", .description = "Assume that the transactional-execution facility is installed", diff --git a/lib/std/target/wasm.zig b/lib/std/target/wasm.zig index 72b2b6d431..746a7c12c7 100644 --- a/lib/std/target/wasm.zig +++ b/lib/std/target/wasm.zig @@ -9,6 +9,7 @@ pub const Feature = enum { multivalue, mutable_globals, nontrapping_fptoint, + reference_types, sign_ext, simd128, tail_call, @@ -51,6 +52,11 @@ pub const all_features = blk: { .description = "Enable non-trapping float-to-int conversion operators", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.reference_types)] = .{ + .llvm_name = "reference-types", + .description = "Enable reference types", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.sign_ext)] = .{ .llvm_name = "sign-ext", .description = "Enable sign extension operators", @@ -87,10 +93,12 @@ pub const cpu = struct { .llvm_name = "bleeding-edge", .features = featureSet(&[_]Feature{ .atomics, + .bulk_memory, .mutable_globals, .nontrapping_fptoint, .sign_ext, .simd128, + .tail_call, }), }; pub const generic = CpuModel{ diff --git a/lib/std/target/x86.zig b/lib/std/target/x86.zig index bfcd1abc1a..83e198751f 100644 --- a/lib/std/target/x86.zig +++ b/lib/std/target/x86.zig @@ -8,6 +8,9 @@ pub const Feature = enum { @"64bit", adx, aes, + amx_bf16, + amx_int8, + amx_tile, avx, avx2, avx512bf16, @@ -42,6 +45,7 @@ pub const Feature = enum { false_deps_popcnt, fast_11bytenop, fast_15bytenop, + fast_7bytenop, fast_bextr, fast_gather, fast_hops, @@ -62,6 +66,8 @@ pub const Feature = enum { invpcid, lea_sp, lea_uses_ag, + lvi_cfi, + lvi_load_hardening, lwp, lzcnt, macrofusion, @@ -93,6 +99,8 @@ pub const Feature = enum { retpoline_indirect_calls, rtm, sahf, + serialize, + seses, sgx, sha, shstk, @@ -115,6 +123,7 @@ pub const Feature = enum { sse4a, ssse3, tbm, + tsxldtrk, use_aa, use_glm_div_sqrt_costs, vaes, @@ -167,6 +176,25 @@ pub const all_features = blk: { .sse2, }), }; + result[@enumToInt(Feature.amx_bf16)] = .{ + .llvm_name = "amx-bf16", + .description = "Support AMX-BF16 instructions", + .dependencies = featureSet(&[_]Feature{ + .amx_tile, + }), + }; + result[@enumToInt(Feature.amx_int8)] = .{ + .llvm_name = "amx-int8", + .description = "Support AMX-INT8 instructions", + .dependencies = featureSet(&[_]Feature{ + .amx_tile, + }), + }; + result[@enumToInt(Feature.amx_tile)] = .{ + .llvm_name = "amx-tile", + .description = "Support AMX-TILE instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.avx)] = .{ .llvm_name = "avx", .description = "Enable AVX instructions", @@ -377,6 +405,11 @@ pub const all_features = blk: { .description = "Target can quickly decode up to 15 byte NOPs", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.fast_7bytenop)] = .{ + .llvm_name = "fast-7bytenop", + .description = "Target can quickly decode up to 7 byte NOPs", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.fast_bextr)] = .{ .llvm_name = "fast-bextr", .description = "Indicates that the BEXTR instruction is implemented as a single uop with good throughput", @@ -484,6 +517,16 @@ pub const all_features = blk: { .description = "LEA instruction needs inputs at AG stage", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.lvi_cfi)] = .{ + .llvm_name = "lvi-cfi", + .description = "Prevent indirect calls/branches from using a memory operand, and precede all indirect calls/branches from a register with an LFENCE instruction to serialize control flow. Also decompose RET instructions into a POP+LFENCE+JMP sequence.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.lvi_load_hardening)] = .{ + .llvm_name = "lvi-load-hardening", + .description = "Insert LFENCE instructions to prevent data speculatively injected into loads from being used maliciously.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.lwp)] = .{ .llvm_name = "lwp", .description = "Enable LWP instructions", @@ -646,6 +689,18 @@ pub const all_features = blk: { .description = "Support LAHF and SAHF instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.serialize)] = .{ + .llvm_name = "serialize", + .description = "Has serialize instruction", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.seses)] = .{ + .llvm_name = "seses", + .description = "Prevent speculative execution side channel timing attacks by inserting a speculation barrier before memory reads, memory writes, and conditional branches. Implies LVI Control Flow integrity.", + .dependencies = featureSet(&[_]Feature{ + .lvi_cfi, + }), + }; result[@enumToInt(Feature.sgx)] = .{ .llvm_name = "sgx", .description = "Enable Software Guard Extensions", @@ -770,6 +825,11 @@ pub const all_features = blk: { .description = "Enable TBM instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.tsxldtrk)] = .{ + .llvm_name = "tsxldtrk", + .description = "Support TSXLDTRK instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.use_aa)] = .{ .llvm_name = "use-aa", .description = "Use alias analysis during codegen", @@ -831,17 +891,23 @@ pub const all_features = blk: { result[@enumToInt(Feature.xsavec)] = .{ .llvm_name = "xsavec", .description = "Support xsavec instructions", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .xsave, + }), }; result[@enumToInt(Feature.xsaveopt)] = .{ .llvm_name = "xsaveopt", .description = "Support xsaveopt instructions", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .xsave, + }), }; result[@enumToInt(Feature.xsaves)] = .{ .llvm_name = "xsaves", .description = "Support xsaves instructions", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .xsave, + }), }; const ti = @typeInfo(Feature); for (result) |*elem, i| { @@ -866,6 +932,7 @@ pub const cpu = struct { .lzcnt, .nopl, .popcnt, + .prfchw, .sahf, .slow_shld, .sse4a, @@ -1043,6 +1110,7 @@ pub const cpu = struct { .lzcnt, .nopl, .popcnt, + .prfchw, .sahf, .slow_shld, .sse4a, @@ -1169,11 +1237,13 @@ pub const cpu = struct { .lwp, .lzcnt, .mmx, + .movbe, .mwaitx, .nopl, .pclmul, .popcnt, .prfchw, + .rdrnd, .sahf, .slow_shld, .tbm, @@ -1226,6 +1296,7 @@ pub const cpu = struct { .f16c, .false_deps_lzcnt_tzcnt, .false_deps_popcnt, + .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, .fast_variable_shuffle, @@ -1362,6 +1433,7 @@ pub const cpu = struct { .cx8, .ermsb, .f16c, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -1423,6 +1495,7 @@ pub const cpu = struct { .ermsb, .f16c, .false_deps_popcnt, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -1483,6 +1556,7 @@ pub const cpu = struct { .ermsb, .f16c, .false_deps_popcnt, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -1528,6 +1602,7 @@ pub const cpu = struct { .cx8, .f16c, .false_deps_popcnt, + .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, .fsgsbase, @@ -1566,6 +1641,7 @@ pub const cpu = struct { .f16c, .false_deps_lzcnt_tzcnt, .false_deps_popcnt, + .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, .fast_variable_shuffle, @@ -1640,6 +1716,7 @@ pub const cpu = struct { .cx16, .cx8, .false_deps_popcnt, + .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, .fxsr, @@ -1773,6 +1850,7 @@ pub const cpu = struct { .f16c, .false_deps_lzcnt_tzcnt, .false_deps_popcnt, + .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, .fast_variable_shuffle, @@ -1867,6 +1945,7 @@ pub const cpu = struct { .cx8, .ermsb, .f16c, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -1936,6 +2015,7 @@ pub const cpu = struct { .cx8, .ermsb, .f16c, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -1989,6 +2069,7 @@ pub const cpu = struct { .cx8, .f16c, .false_deps_popcnt, + .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, .fsgsbase, @@ -2414,6 +2495,7 @@ pub const cpu = struct { .cx16, .cx8, .false_deps_popcnt, + .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, .fxsr, @@ -2443,6 +2525,7 @@ pub const cpu = struct { .cx16, .cx8, .false_deps_popcnt, + .fast_7bytenop, .fxsr, .idivq_to_divl, .mmx, @@ -2487,6 +2570,7 @@ pub const cpu = struct { .ermsb, .f16c, .false_deps_popcnt, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -2539,6 +2623,7 @@ pub const cpu = struct { .ermsb, .f16c, .false_deps_popcnt, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -2596,6 +2681,7 @@ pub const cpu = struct { .ermsb, .f16c, .false_deps_popcnt, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -2639,6 +2725,7 @@ pub const cpu = struct { .cx16, .cx8, .false_deps_popcnt, + .fast_7bytenop, .fxsr, .idivq_to_divl, .mmx, @@ -2689,6 +2776,7 @@ pub const cpu = struct { .cx8, .ermsb, .f16c, + .fast_15bytenop, .fast_gather, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -2738,8 +2826,8 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .aes, - .cldemote, .clflushopt, + .clwb, .cmov, .cx16, .cx8, @@ -2748,8 +2836,6 @@ pub const cpu = struct { .gfni, .mmx, .movbe, - .movdir64b, - .movdiri, .nopl, .pclmul, .popcnt, @@ -2768,7 +2854,6 @@ pub const cpu = struct { .ssse3, .use_glm_div_sqrt_costs, .vzeroupper, - .waitpkg, .x87, .xsave, .xsavec, @@ -2824,6 +2909,7 @@ pub const cpu = struct { .cmov, .cx8, .fxsr, + .idivq_to_divl, .macrofusion, .mmx, .nopl,