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std.Target: Remove Cpu.Arch.propeller2 and use a CPU feature instead.
This commit is contained in:
Alex Rønne Petersen
parent
5248f0a909
commit
2fe32ef847
@ -763,6 +763,7 @@ pub const mips = @import("Target/mips.zig");
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pub const msp430 = @import("Target/msp430.zig");
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pub const nvptx = @import("Target/nvptx.zig");
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pub const powerpc = @import("Target/powerpc.zig");
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pub const propeller = @import("Target/propeller.zig");
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pub const riscv = @import("Target/riscv.zig");
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pub const sparc = @import("Target/sparc.zig");
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pub const spirv = @import("Target/spirv.zig");
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@ -772,7 +773,6 @@ pub const wasm = @import("Target/wasm.zig");
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pub const x86 = @import("Target/x86.zig");
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pub const xcore = @import("Target/xcore.zig");
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pub const xtensa = @import("Target/xtensa.zig");
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pub const propeller = @import("Target/propeller.zig");
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pub const Abi = enum {
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none,
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@ -1081,6 +1081,7 @@ pub fn toElfMachine(target: Target) std.elf.EM {
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.msp430 => .MSP430,
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.powerpc, .powerpcle => .PPC,
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.powerpc64, .powerpc64le => .PPC64,
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.propeller => .PROPELLER,
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.riscv32, .riscv64 => .RISCV,
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.s390x => .S390,
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.sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,
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@ -1091,9 +1092,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {
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.xcore => .XCORE,
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.xtensa => .XTENSA,
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.propeller1 => .PROPELLER,
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.propeller2 => .PROPELLER2,
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.nvptx,
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.nvptx64,
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.spirv,
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@ -1152,8 +1150,7 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
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.wasm64,
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.xcore,
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.xtensa,
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.propeller1,
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.propeller2,
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.propeller,
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=> .UNKNOWN,
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};
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}
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@ -1366,8 +1363,7 @@ pub const Cpu = struct {
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powerpcle,
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powerpc64,
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powerpc64le,
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propeller1,
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propeller2,
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propeller,
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riscv32,
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riscv64,
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s390x,
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@ -1517,14 +1513,6 @@ pub const Cpu = struct {
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};
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}
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/// Returns if the architecture is a Parallax propeller architecture.
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pub inline fn isPropeller(arch: Arch) bool {
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return switch (arch) {
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.propeller1, .propeller2 => true,
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else => false,
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};
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}
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pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
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for (arch.allCpuModels()) |cpu| {
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if (std.mem.eql(u8, cpu_name, cpu.name)) {
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@ -1568,8 +1556,7 @@ pub const Cpu = struct {
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.loongarch32,
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.loongarch64,
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.arc,
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.propeller1,
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.propeller2,
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.propeller,
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=> .little,
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.armeb,
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@ -1604,8 +1591,8 @@ pub const Cpu = struct {
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.flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
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// Propeller address spaces:
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.cog, .hub => arch.isPropeller(),
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.lut => (arch == .propeller2),
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.cog, .hub => arch == .propeller,
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.lut => arch == .propeller, // TODO: This should check for the `p2` CPU feature.
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};
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}
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@ -1618,6 +1605,7 @@ pub const Cpu = struct {
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.loongarch32, .loongarch64 => "loongarch",
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.mips, .mipsel, .mips64, .mips64el => "mips",
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.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
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.propeller => "propeller",
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.riscv32, .riscv64 => "riscv",
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.sparc, .sparc64 => "sparc",
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.s390x => "s390x",
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@ -1625,7 +1613,6 @@ pub const Cpu = struct {
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.nvptx, .nvptx64 => "nvptx",
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.wasm32, .wasm64 => "wasm",
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.spirv, .spirv32, .spirv64 => "spirv",
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.propeller1, .propeller2 => "propeller",
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else => @tagName(arch),
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};
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}
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@ -1851,10 +1838,7 @@ pub const Cpu = struct {
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=> &.{.msp430},
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.propeller1_sysv,
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=> &.{.propeller1},
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.propeller2_sysv,
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=> &.{.propeller2},
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=> &.{.propeller},
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.s390x_sysv,
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.s390x_sysv_vx,
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@ -1933,8 +1917,7 @@ pub const Cpu = struct {
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.msp430 => &msp430.cpu.generic,
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.powerpc, .powerpcle => &powerpc.cpu.ppc,
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.powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
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.propeller1 => &propeller.cpu.generic,
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.propeller2 => &propeller.cpu.generic,
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.propeller => &propeller.cpu.p1,
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.riscv32 => &riscv.cpu.generic_rv32,
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.riscv64 => &riscv.cpu.generic_rv64,
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.spirv, .spirv32, .spirv64 => &spirv.cpu.generic,
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@ -2647,8 +2630,7 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
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.spirv32,
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.loongarch32,
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.xtensa,
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.propeller1,
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.propeller2,
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.propeller,
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=> 32,
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.aarch64,
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@ -3159,8 +3141,7 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
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.xcore,
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.kalimba,
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.xtensa,
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.propeller1,
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.propeller2,
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.propeller,
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=> 4,
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.arm,
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@ -3254,8 +3235,7 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
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.xcore,
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.kalimba,
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.xtensa,
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.propeller1,
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.propeller2,
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.propeller,
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=> 4,
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.arc,
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@ -3360,8 +3340,7 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
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else
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.{ .m68k_sysv = .{} },
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.msp430 => .{ .msp430_eabi = .{} },
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.propeller1 => .{ .propeller1_sysv = .{} },
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.propeller2 => .{ .propeller2_sysv = .{} },
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.propeller => .{ .propeller1_sysv = .{} },
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.s390x => .{ .s390x_sysv = .{} },
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.ve => .{ .ve_sysv = .{} },
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.xcore => .{ .xcore_xs1 = .{} },
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@ -1,20 +1,46 @@
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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pub const Feature = enum {};
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pub const Feature = enum {
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p2,
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};
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pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
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pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
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pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
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pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
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pub const all_features: [0]CpuFeature = .{};
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pub const all_features = blk: {
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const len = @typeInfo(Feature).@"enum".fields.len;
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std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
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var result: [len]CpuFeature = undefined;
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result[@intFromEnum(Feature.p2)] = .{
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.llvm_name = null,
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.description = "Enable Propeller 2",
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.dependencies = featureSet(&[_]Feature{}),
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};
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const ti = @typeInfo(Feature);
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for (&result, 0..) |*elem, i| {
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elem.index = i;
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elem.name = ti.@"enum".fields[i].name;
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}
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break :blk result;
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};
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pub const cpu = struct {
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pub const generic = CpuModel{
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.name = "generic",
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pub const p1: CpuModel = .{
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.name = "p1",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{}),
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};
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pub const p2: CpuModel = .{
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.name = "p2",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.p2,
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}),
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};
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};
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@ -371,12 +371,9 @@ pub const CallingConvention = union(enum(u8)) {
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/// The standard `msp430` calling convention.
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msp430_eabi: CommonOptions,
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/// The standard `propeller1` calling convention.
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/// The standard `propeller` calling convention.
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propeller1_sysv: CommonOptions,
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/// The standard `propeller2` calling convention.
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propeller2_sysv: CommonOptions,
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// Calling conventions for the `s390x` architecture.
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s390x_sysv: CommonOptions,
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s390x_sysv_vx: CommonOptions,
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@ -37271,6 +37271,7 @@ pub fn analyzeAsAddressSpace(
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const is_spirv = arch.isSpirV();
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const is_gpu = is_nv or is_amd or is_spirv;
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// TODO: Deduplicate with `std.Target.Cpu.Arch.supportsAddressSpace`.
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const supported = switch (address_space) {
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// TODO: on spir-v only when os is opencl.
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.generic => true,
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@ -37283,8 +37284,8 @@ pub fn analyzeAsAddressSpace(
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// TODO this should also check how many flash banks the cpu has
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.flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
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.cog, .hub => arch.isPropeller(),
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.lut => (arch == .propeller2),
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.cog, .hub => arch == .propeller,
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.lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),
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};
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if (!supported) {
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@ -1647,7 +1647,7 @@ pub fn maxIntAlignment(target: std.Target) u16 {
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.avr => 1,
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.msp430 => 2,
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.xcore => 4,
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.propeller1, .propeller2 => 4,
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.propeller => 4,
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.arm,
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.armeb,
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@ -3619,8 +3619,7 @@ pub fn atomicPtrAlignment(
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.spirv32,
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.loongarch32,
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.xtensa,
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.propeller1,
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.propeller2,
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.propeller,
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=> 32,
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.amdgcn,
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@ -98,8 +98,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
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.ve => "ve",
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.kalimba,
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.propeller1,
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.propeller2,
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.propeller,
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=> unreachable, // Gated by hasLlvmSupport().
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};
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@ -11834,7 +11833,6 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: std.Targ
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.m68k_gnu,
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.msp430_eabi,
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.propeller1_sysv,
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.propeller2_sysv,
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.s390x_sysv,
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.s390x_sysv_vx,
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.ve_sysv,
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@ -13023,8 +13021,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
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// LLVM does does not have a backend for these.
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.kalimba,
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.propeller1,
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.propeller2,
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.propeller,
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=> unreachable,
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}
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}
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@ -195,8 +195,7 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
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// No LLVM backend exists.
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.kalimba,
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.propeller1,
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.propeller2,
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.propeller,
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=> false,
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};
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}
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@ -1016,6 +1016,29 @@ const targets = [_]ArchTarget{
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"ppc32",
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},
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},
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.{
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.zig_name = "propeller",
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.llvm = null,
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.extra_features = &.{
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.{
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.zig_name = "p2",
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.desc = "Enable Propeller 2",
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.deps = &.{},
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},
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},
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.extra_cpus = &.{
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.{
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.llvm_name = null,
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.zig_name = "p1",
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.features = &.{},
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},
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.{
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.llvm_name = null,
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.zig_name = "p2",
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.features = &.{"p2"},
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},
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},
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},
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.{
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.zig_name = "riscv",
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.llvm = .{
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