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std.os.linux: Some adjustments after syscall generation strategy changes.
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@ -474,7 +474,7 @@ pub fn dup2(old: i32, new: i32) usize {
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} else {
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if (old == new) {
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if (std.debug.runtime_safety) {
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const rc = syscall2(.fcntl, @as(usize, @bitCast(@as(isize, old))), F.GETFD);
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const rc = fcntl(F.GETFD, @as(fd_t, old), 0);
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if (@as(isize, @bitCast(rc)) < 0) return rc;
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}
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return @as(usize, @intCast(old));
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@ -1211,7 +1211,7 @@ pub fn llseek(fd: i32, offset: u64, result: ?*u64, whence: usize) usize {
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// NOTE: The offset parameter splitting is independent from the target
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// endianness.
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return syscall5(
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._llseek,
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.llseek,
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@as(usize, @bitCast(@as(isize, fd))),
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@as(usize, @truncate(offset >> 32)),
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@as(usize, @truncate(offset)),
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@ -1370,7 +1370,11 @@ pub fn waitid(id_type: P, id: i32, infop: *siginfo_t, flags: u32) usize {
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}
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pub fn fcntl(fd: fd_t, cmd: i32, arg: usize) usize {
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return syscall3(.fcntl, @as(usize, @bitCast(@as(isize, fd))), @as(usize, @bitCast(@as(isize, cmd))), arg);
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if (@hasField(SYS, "fcntl64")) {
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return syscall3(.fcntl64, @as(usize, @bitCast(@as(isize, fd))), @as(usize, @bitCast(@as(isize, cmd))), arg);
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} else {
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return syscall3(.fcntl, @as(usize, @bitCast(@as(isize, fd))), @as(usize, @bitCast(@as(isize, cmd))), arg);
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}
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}
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pub fn flock(fd: fd_t, operation: i32) usize {
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@ -2198,8 +2202,24 @@ pub fn process_vm_writev(pid: pid_t, local: []const iovec_const, remote: []const
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}
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pub fn fadvise(fd: fd_t, offset: i64, len: i64, advice: usize) usize {
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if (comptime builtin.cpu.arch.isMIPS()) {
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// MIPS requires a 7 argument syscall
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if (comptime native_arch.isARM() or native_arch.isPPC()) {
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// These architectures reorder the arguments so that a register is not skipped to align the
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// register number that `offset` is passed in.
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const offset_halves = splitValue64(offset);
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const length_halves = splitValue64(len);
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return syscall6(
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.fadvise64_64,
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@as(usize, @bitCast(@as(isize, fd))),
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advice,
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offset_halves[0],
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offset_halves[1],
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length_halves[0],
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length_halves[1],
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);
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} else if (comptime native_arch == .mips or native_arch == .mipsel) {
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// MIPS O32 does not deal with the register alignment issue, so pass a dummy value.
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const offset_halves = splitValue64(offset);
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const length_halves = splitValue64(len);
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@ -2214,24 +2234,8 @@ pub fn fadvise(fd: fd_t, offset: i64, len: i64, advice: usize) usize {
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length_halves[1],
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advice,
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);
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} else if (comptime builtin.cpu.arch.isARM()) {
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// ARM reorders the arguments
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const offset_halves = splitValue64(offset);
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const length_halves = splitValue64(len);
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return syscall6(
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.fadvise64_64,
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@as(usize, @bitCast(@as(isize, fd))),
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advice,
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offset_halves[0],
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offset_halves[1],
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length_halves[0],
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length_halves[1],
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);
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} else if (@hasField(SYS, "fadvise64_64") and usize_bits != 64) {
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// The extra usize check is needed to avoid SPARC64 because it provides both
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// fadvise64 and fadvise64_64 but the latter behaves differently than other platforms.
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} else if (comptime usize_bits < 64) {
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// Other 32-bit architectures do not require register alignment.
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const offset_halves = splitValue64(offset);
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const length_halves = splitValue64(len);
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@ -2246,8 +2250,18 @@ pub fn fadvise(fd: fd_t, offset: i64, len: i64, advice: usize) usize {
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advice,
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);
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} else {
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// On 64-bit architectures, fadvise64_64 and fadvise64 are the same. Generally, older ports
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// call it fadvise64 (x86, PowerPC, etc), while newer ports call it fadvise64_64 (RISC-V,
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// LoongArch, etc). SPARC is the odd one out because it has both.
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return syscall4(
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.fadvise64,
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// 64-bit SPARC (apparently?) has a broken fadvise64_64, so use its fadvise64 instead.
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// TODO: I can't make sense of this. They go to the same code in the kernel, and there
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// is no special-casing for SPARC in glibc and musl. I suspect a QEMU bug, which is
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// really not our responsibility.
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if (@hasField(SYS, "fadvise64_64") and native_arch != .sparc64)
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.fadvise64_64
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else
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.fadvise64,
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@as(usize, @bitCast(@as(isize, fd))),
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@as(usize, @bitCast(offset)),
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@as(usize, @bitCast(len)),
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