mirror of
https://github.com/ziglang/zig.git
synced 2026-01-20 14:25:16 +00:00
x86_64: implement integer vector movement
This commit is contained in:
Jacob Young
parent
f83ebd8e6c
commit
2cbd442a9d
@ -8579,56 +8579,174 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAirResult(inst, result);
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}
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fn movMirTag(self: *Self, ty: Type, aligned: bool) !Mir.Inst.FixedTag {
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const MoveStrategy = union(enum) {
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move: Mir.Inst.FixedTag,
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insert_extract: InsertExtract,
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vex_insert_extract: InsertExtract,
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const InsertExtract = struct {
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insert: Mir.Inst.FixedTag,
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extract: Mir.Inst.FixedTag,
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imm: Immediate,
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};
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};
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fn moveStrategy(self: *Self, ty: Type, aligned: bool) !MoveStrategy {
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switch (ty.zigTypeTag()) {
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else => return .{ ._, .mov },
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else => return .{ .move = .{ ._, .mov } },
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.Float => switch (ty.floatBits(self.target.*)) {
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16 => unreachable, // needs special handling
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32 => return if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov },
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64 => return if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov },
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128 => return if (self.hasFeature(.avx))
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16 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
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.insert = .{ .vp_w, .insr },
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.extract = .{ .vp_w, .extr },
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.imm = Immediate.u(0),
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} } else .{ .insert_extract = .{
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.insert = .{ .p_w, .insr },
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.extract = .{ .p_w, .extr },
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.imm = Immediate.u(0),
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} },
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32 => return .{ .move = if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov } },
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64 => return .{ .move = if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov } },
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128 => return .{ .move = if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
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else => {},
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},
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.Vector => switch (ty.childType().zigTypeTag()) {
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.Float => switch (ty.childType().floatBits(self.target.*)) {
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.Int => switch (ty.childType().intInfo(self.target.*).bits) {
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8 => switch (ty.vectorLen()) {
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1 => if (self.hasFeature(.avx)) return .{ .vex_insert_extract = .{
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.insert = .{ .vp_b, .insr },
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.extract = .{ .vp_b, .extr },
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.imm = Immediate.u(0),
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} } else if (self.hasFeature(.sse4_2)) return .{ .insert_extract = .{
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.insert = .{ .p_b, .insr },
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.extract = .{ .p_b, .extr },
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.imm = Immediate.u(0),
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} },
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2 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
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.insert = .{ .vp_w, .insr },
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.extract = .{ .vp_w, .extr },
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.imm = Immediate.u(0),
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} } else .{ .insert_extract = .{
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.insert = .{ .p_w, .insr },
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.extract = .{ .p_w, .extr },
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.imm = Immediate.u(0),
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} },
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3...4 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_ss, .mov }
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else
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.{ ._ss, .mov } },
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5...8 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_sd, .mov }
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else
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.{ ._sd, .mov } },
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else => {},
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},
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16 => switch (ty.vectorLen()) {
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1 => unreachable, // needs special handling
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2 => return if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov },
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3...4 => return if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov },
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5...8 => return if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
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9...16 => if (self.hasFeature(.avx))
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return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
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1 => return if (self.hasFeature(.avx)) .{ .vex_insert_extract = .{
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.insert = .{ .vp_w, .insr },
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.extract = .{ .vp_w, .extr },
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.imm = Immediate.u(0),
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} } else .{ .insert_extract = .{
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.insert = .{ .p_w, .insr },
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.extract = .{ .p_w, .extr },
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.imm = Immediate.u(0),
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} },
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2 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_ss, .mov }
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else
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.{ ._ss, .mov } },
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3...4 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_sd, .mov }
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else
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.{ ._sd, .mov } },
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5...8 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_ps, .mov }
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else
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.{ ._ps, .mov } },
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else => {},
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},
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32 => switch (ty.vectorLen()) {
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1 => return if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov },
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2 => return if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov },
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3...4 => return if (self.hasFeature(.avx))
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1 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_ss, .mov }
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else
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.{ ._ss, .mov } },
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2 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_sd, .mov }
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else
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.{ ._sd, .mov } },
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3...4 => return .{ .move = if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
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5...8 => if (self.hasFeature(.avx))
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return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
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return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
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else => {},
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},
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64 => switch (ty.vectorLen()) {
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1 => return if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov },
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2 => return if (self.hasFeature(.avx))
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1 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_sd, .mov }
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else
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.{ ._sd, .mov } },
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2 => return .{ .move = if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
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3...4 => if (self.hasFeature(.avx))
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return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
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return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
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else => {},
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},
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else => {},
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},
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.Float => switch (ty.childType().floatBits(self.target.*)) {
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16 => switch (ty.vectorLen()) {
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1 => {},
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2 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_ss, .mov }
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else
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.{ ._ss, .mov } },
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3...4 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_sd, .mov }
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else
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.{ ._sd, .mov } },
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5...8 => return .{ .move = if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
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9...16 => if (self.hasFeature(.avx))
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return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
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else => {},
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},
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32 => switch (ty.vectorLen()) {
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1 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_ss, .mov }
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else
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.{ ._ss, .mov } },
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2 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_sd, .mov }
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else
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.{ ._sd, .mov } },
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3...4 => return .{ .move = if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
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5...8 => if (self.hasFeature(.avx))
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return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
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else => {},
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},
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64 => switch (ty.vectorLen()) {
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1 => return .{ .move = if (self.hasFeature(.avx))
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.{ .v_sd, .mov }
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else
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.{ ._sd, .mov } },
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2 => return .{ .move = if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
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3...4 => if (self.hasFeature(.avx))
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return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
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else => {},
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},
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128 => switch (ty.vectorLen()) {
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1 => return if (self.hasFeature(.avx))
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1 => return .{ .move = if (self.hasFeature(.avx))
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if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
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else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu } },
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2 => if (self.hasFeature(.avx))
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return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
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return .{ .move = if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu } },
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else => {},
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},
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else => {},
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@ -8636,7 +8754,7 @@ fn movMirTag(self: *Self, ty: Type, aligned: bool) !Mir.Inst.FixedTag {
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else => {},
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},
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}
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return self.fail("TODO movMirTag for {}", .{ty.fmt(self.bin_file.options.module.?)});
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return self.fail("TODO moveStrategy for {}", .{ty.fmt(self.bin_file.options.module.?)});
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}
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fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError!void {
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@ -8764,6 +8882,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
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.load_frame,
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.lea_frame,
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=> {
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const dst_alias = registerAlias(dst_reg, abi_size);
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const src_mem = Memory.sib(Memory.PtrSize.fromSize(abi_size), switch (src_mcv) {
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.register_offset, .indirect => |reg_off| .{
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.base = .{ .reg = reg_off.reg },
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@ -8775,71 +8894,81 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
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},
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else => unreachable,
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});
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if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
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try self.asmRegisterMemoryImmediate(
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.{ .p_w, .insr },
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registerAlias(dst_reg, abi_size),
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switch (@as(MoveStrategy, switch (src_mcv) {
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.register_offset => |reg_off| switch (reg_off.off) {
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0 => return self.genSetReg(dst_reg, ty, .{ .register = reg_off.reg }),
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else => .{ .move = .{ ._, .lea } },
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},
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.indirect => try self.moveStrategy(ty, false),
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.load_frame => |frame_addr| try self.moveStrategy(
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ty,
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self.getFrameAddrAlignment(frame_addr) >= ty.abiAlignment(self.target.*),
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),
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.lea_frame => .{ .move = .{ ._, .lea } },
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else => unreachable,
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})) {
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.move => |tag| try self.asmRegisterMemory(tag, dst_alias, src_mem),
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.insert_extract => |ie| try self.asmRegisterMemoryImmediate(
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ie.insert,
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dst_alias,
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src_mem,
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Immediate.u(0),
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)
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else
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try self.asmRegisterMemory(
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switch (src_mcv) {
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.register_offset => |reg_off| switch (reg_off.off) {
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0 => return self.genSetReg(dst_reg, ty, .{ .register = reg_off.reg }),
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else => .{ ._, .lea },
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},
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.indirect => try self.movMirTag(ty, false),
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.load_frame => |frame_addr| try self.movMirTag(
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ty,
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self.getFrameAddrAlignment(frame_addr) >= ty.abiAlignment(self.target.*),
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),
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.lea_frame => .{ ._, .lea },
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else => unreachable,
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},
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registerAlias(dst_reg, abi_size),
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ie.imm,
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),
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.vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
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ie.insert,
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dst_alias,
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dst_alias,
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src_mem,
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);
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ie.imm,
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),
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}
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},
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.memory, .load_direct, .load_got, .load_tlv => {
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switch (src_mcv) {
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.memory => |addr| if (math.cast(i32, @bitCast(i64, addr))) |small_addr| {
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const dst_alias = registerAlias(dst_reg, abi_size);
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const src_mem = Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
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.base = .{ .reg = .ds },
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.disp = small_addr,
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});
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return if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
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self.asmRegisterMemoryImmediate(
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.{ .p_w, .insr },
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registerAlias(dst_reg, abi_size),
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switch (try self.moveStrategy(ty, mem.isAlignedGeneric(
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u32,
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@bitCast(u32, small_addr),
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ty.abiAlignment(self.target.*),
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))) {
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.move => |tag| try self.asmRegisterMemory(tag, dst_alias, src_mem),
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.insert_extract => |ie| try self.asmRegisterMemoryImmediate(
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ie.insert,
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dst_alias,
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src_mem,
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Immediate.u(0),
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)
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else
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self.asmRegisterMemory(
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try self.movMirTag(ty, mem.isAlignedGeneric(
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u32,
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@bitCast(u32, small_addr),
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ty.abiAlignment(self.target.*),
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)),
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registerAlias(dst_reg, abi_size),
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ie.imm,
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),
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.vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
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ie.insert,
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dst_alias,
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dst_alias,
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src_mem,
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);
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ie.imm,
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),
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}
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},
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.load_direct => |sym_index| if (!ty.isRuntimeFloat()) {
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const atom_index = try self.owner.getSymbolIndex(self);
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = .direct_reloc,
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.data = .{ .rx = .{
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.r1 = dst_reg.to64(),
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.payload = try self.addExtra(Mir.Reloc{
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.atom_index = atom_index,
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.sym_index = sym_index,
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}),
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} },
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});
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return;
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.load_direct => |sym_index| switch (ty.zigTypeTag()) {
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else => {
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const atom_index = try self.owner.getSymbolIndex(self);
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = .direct_reloc,
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.data = .{ .rx = .{
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.r1 = dst_reg.to64(),
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.payload = try self.addExtra(Mir.Reloc{
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.atom_index = atom_index,
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.sym_index = sym_index,
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}),
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} },
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});
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return;
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},
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.Float, .Vector => {},
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},
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.load_got, .load_tlv => {},
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else => unreachable,
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@ -8849,22 +8978,26 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
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const addr_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
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defer self.register_manager.unlockReg(addr_lock);
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const dst_alias = registerAlias(dst_reg, abi_size);
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const src_mem = Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
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.base = .{ .reg = addr_reg },
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});
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if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
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try self.asmRegisterMemoryImmediate(
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.{ .p_w, .insr },
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registerAlias(dst_reg, abi_size),
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switch (try self.moveStrategy(ty, false)) {
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.move => |tag| try self.asmRegisterMemory(tag, dst_alias, src_mem),
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.insert_extract => |ie| try self.asmRegisterMemoryImmediate(
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ie.insert,
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dst_alias,
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src_mem,
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Immediate.u(0),
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)
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else
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try self.asmRegisterMemory(
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try self.movMirTag(ty, false),
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registerAlias(dst_reg, abi_size),
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ie.imm,
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),
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.vex_insert_extract => |ie| try self.asmRegisterRegisterMemoryImmediate(
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ie.insert,
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dst_alias,
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||||
dst_alias,
|
||||
src_mem,
|
||||
);
|
||||
ie.imm,
|
||||
),
|
||||
}
|
||||
},
|
||||
.lea_direct, .lea_got => |sym_index| {
|
||||
const atom_index = try self.owner.getSymbolIndex(self);
|
||||
@ -8966,36 +9099,33 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
|
||||
Memory.PtrSize.fromSize(abi_size),
|
||||
.{ .base = base, .disp = disp },
|
||||
);
|
||||
if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
|
||||
try self.asmMemoryRegisterImmediate(
|
||||
.{ .p_w, .extr },
|
||||
const src_alias = registerAlias(src_reg, abi_size);
|
||||
switch (try self.moveStrategy(ty, switch (base) {
|
||||
.none => mem.isAlignedGeneric(
|
||||
u32,
|
||||
@bitCast(u32, disp),
|
||||
ty.abiAlignment(self.target.*),
|
||||
),
|
||||
.reg => |reg| switch (reg) {
|
||||
.es, .cs, .ss, .ds => mem.isAlignedGeneric(
|
||||
u32,
|
||||
@bitCast(u32, disp),
|
||||
ty.abiAlignment(self.target.*),
|
||||
),
|
||||
else => false,
|
||||
},
|
||||
.frame => |frame_index| self.getFrameAddrAlignment(
|
||||
.{ .index = frame_index, .off = disp },
|
||||
) >= ty.abiAlignment(self.target.*),
|
||||
})) {
|
||||
.move => |tag| try self.asmMemoryRegister(tag, dst_mem, src_alias),
|
||||
.insert_extract, .vex_insert_extract => |ie| try self.asmMemoryRegisterImmediate(
|
||||
ie.extract,
|
||||
dst_mem,
|
||||
src_reg.to128(),
|
||||
Immediate.u(0),
|
||||
)
|
||||
else
|
||||
try self.asmMemoryRegister(
|
||||
try self.movMirTag(ty, switch (base) {
|
||||
.none => mem.isAlignedGeneric(
|
||||
u32,
|
||||
@bitCast(u32, disp),
|
||||
ty.abiAlignment(self.target.*),
|
||||
),
|
||||
.reg => |reg| switch (reg) {
|
||||
.es, .cs, .ss, .ds => mem.isAlignedGeneric(
|
||||
u32,
|
||||
@bitCast(u32, disp),
|
||||
ty.abiAlignment(self.target.*),
|
||||
),
|
||||
else => false,
|
||||
},
|
||||
.frame => |frame_index| self.getFrameAddrAlignment(
|
||||
.{ .index = frame_index, .off = disp },
|
||||
) >= ty.abiAlignment(self.target.*),
|
||||
}),
|
||||
dst_mem,
|
||||
registerAlias(src_reg, abi_size),
|
||||
);
|
||||
src_alias,
|
||||
ie.imm,
|
||||
),
|
||||
}
|
||||
},
|
||||
.register_overflow => |ro| {
|
||||
try self.genSetMem(
|
||||
|
||||
@ -146,7 +146,6 @@ test "@min/@max more than two arguments" {
|
||||
|
||||
test "@min/@max more than two vector arguments" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -1129,7 +1129,6 @@ test "loading the second vector from a slice of vectors" {
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
|
||||
@setRuntimeSafety(false);
|
||||
var small_bases = [2]@Vector(2, u8){
|
||||
@ -1219,7 +1218,6 @@ test "zero multiplicand" {
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
|
||||
const zeros = @Vector(2, u32){ 0.0, 0.0 };
|
||||
var ones = @Vector(2, u32){ 1.0, 1.0 };
|
||||
@ -1324,7 +1322,6 @@ test "store to vector in slice" {
|
||||
test "addition of vectors represented as strings" {
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
|
||||
const V = @Vector(3, u8);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user