std.Target: add Arch tag and info for kvx

lib/compiler/aro/aro/target.zig

@@ -477,6 +477,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .ve,
         .bpfel,
         .bpfeb,
+        .kvx,
         .s390x,
         => return null,
 
@@ -551,6 +552,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .nvptx64,
         .wasm64,
         .spirv64,
+        .kvx,
         .loongarch64,
         .mips64,
         .mips64el,
@@ -636,8 +638,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .wasm32 => "wasm32",
         .wasm64 => "wasm64",
         .ve => "ve",
-        // Note: propeller1, kalimba and or1k are not supported in LLVM; this is the Zig arch name
+        // Note: propeller1, kalimba, kvx, and or1k are not supported in LLVM; this is the Zig arch name
         .kalimba => "kalimba",
+        .kvx => "kvx",
         .propeller => "propeller",
         .or1k => "or1k",
     };

lib/std/Target.zig

@@ -710,6 +710,7 @@ pub const csky = @import("Target/csky.zig");
 pub const hexagon = @import("Target/hexagon.zig");
 pub const hppa = @import("Target/generic.zig");
 pub const kalimba = @import("Target/generic.zig");
+pub const kvx = @import("Target/kvx.zig");
 pub const lanai = @import("Target/lanai.zig");
 pub const loongarch = @import("Target/loongarch.zig");
 pub const m68k = @import("Target/m68k.zig");
@@ -1043,6 +1044,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
         .hexagon => .QDSP6,
         .hppa, .hppa64 => .PARISC,
         .kalimba => .CSR_KALIMBA,
+        .kvx => .KVX,
         .lanai => .LANAI,
         .loongarch32, .loongarch64 => .LOONGARCH,
         .m68k => .@"68K",
@@ -1105,6 +1107,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
         .hppa,
         .hppa64,
         .kalimba,
+        .kvx,
         .lanai,
         .m68k,
         .microblaze,
@@ -1310,6 +1313,7 @@ pub const Cpu = struct {
         hppa,
         hppa64,
         kalimba,
+        kvx,
         lanai,
         loongarch32,
         loongarch64,
@@ -1385,6 +1389,7 @@ pub const Cpu = struct {
             hexagon,
             hppa,
             kalimba,
+            kvx,
             lanai,
             loongarch,
             m68k,
@@ -1420,6 +1425,7 @@ pub const Cpu = struct {
                 .hexagon => .hexagon,
                 .hppa, .hppa64 => .hppa,
                 .kalimba => .kalimba,
+                .kvx => .kvx,
                 .lanai => .lanai,
                 .loongarch32, .loongarch64 => .loongarch,
                 .m68k => .m68k,
@@ -1623,6 +1629,7 @@ pub const Cpu = struct {
                 .csky,
                 .hexagon,
                 .kalimba,
+                .kvx,
                 .loongarch32,
                 .loongarch64,
                 .microblazeel,
@@ -1847,6 +1854,10 @@ pub const Cpu = struct {
                 .hppa64_elf,
                 => &.{.hppa64},
 
+                .kvx_lp64,
+                .kvx_ilp32,
+                => &.{.kvx},
+
                 .lanai_sysv,
                 => &.{.lanai},
 
@@ -1936,6 +1947,7 @@ pub const Cpu = struct {
             return switch (arch) {
                 .amdgcn => &amdgcn.cpu.gfx600,
                 .avr => &avr.cpu.avr1,
+                .kvx => &kvx.cpu.coolidge_v1,
                 .loongarch32 => &loongarch.cpu.generic_la32,
                 .loongarch64 => &loongarch.cpu.generic_la64,
                 .mips, .mipsel => &mips.cpu.mips32,
@@ -1987,6 +1999,7 @@ pub const Cpu = struct {
                 .bpfel, .bpfeb => &bpf.cpu.v3,
                 .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
                 .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
+                .kvx => &kvx.cpu.coolidge_v2,
                 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
                 .loongarch64 => &loongarch.cpu.la64v1_0,
                 .m68k => &m68k.cpu.M68000,
@@ -2440,6 +2453,7 @@ pub const DynamicLinker = struct {
                     .aarch64,
                     .aarch64_be,
                     .hexagon,
+                    .kvx,
                     .m68k,
                     .microblaze,
                     .microblazeel,
@@ -2817,6 +2831,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
         .bpfeb,
         .bpfel,
         .hppa64,
+        .kvx,
         .loongarch64,
         .mips64,
         .mips64el,
@@ -3375,6 +3390,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
             .aarch64_be,
             .alpha,
             .hppa64,
+            .kvx,
             .loongarch32,
             .loongarch64,
             .mips64,
@@ -3482,6 +3498,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
             .aarch64_be,
             .alpha,
             .hppa64,
+            .kvx,
             .loongarch32,
             .loongarch64,
             .mips64,
@@ -3557,6 +3574,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
         .bpfel,
         .bpfeb,
         .hppa64,
+        .kvx,
         .loongarch64,
         .mips64,
         .mips64el,
@@ -3626,6 +3644,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
         .hppa => .{ .hppa_elf = .{} },
         .hppa64 => .{ .hppa64_elf = .{} },
         .kalimba => null,
+        .kvx => switch (target.abi) {
+            .ilp32 => .{ .kvx_ilp32 = .{} },
+            else => .{ .kvx_lp64 = .{} },
+        },
         .lanai => .{ .lanai_sysv = .{} },
         .loongarch64 => .{ .loongarch64_lp64 = .{} },
         .loongarch32 => .{ .loongarch32_ilp32 = .{} },

lib/std/Target/kvx.zig

@@ -0,0 +1,64 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    v3_1,
+    v3_2,
+    v4_1,
+};
+
+pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).@"enum".fields.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@intFromEnum(Feature.v3_1)] = .{
+        .llvm_name = null,
+        .description = "Enable ISA v3.1",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@intFromEnum(Feature.v3_2)] = .{
+        .llvm_name = null,
+        .description = "Enable ISA v3.2",
+        .dependencies = featureSet(&[_]Feature{
+            .v3_1,
+        }),
+    };
+    result[@intFromEnum(Feature.v4_1)] = .{
+        .llvm_name = null,
+        .description = "Enable ISA v4.1",
+        .dependencies = featureSet(&[_]Feature{
+            .v3_2,
+        }),
+    };
+    const ti = @typeInfo(Feature);
+    for (&result, 0..) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.@"enum".fields[i].name;
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const coolidge_v1: CpuModel = .{
+        .name = "coolidge_v1",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v3_1,
+        }),
+    };
+    pub const coolidge_v2: CpuModel = .{
+        .name = "coolidge_v2",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v3_2,
+        }),
+    };
+};

lib/std/builtin.zig

@@ -274,6 +274,9 @@ pub const CallingConvention = union(enum(u8)) {
     /// The standard `hppa64` calling convention.
     hppa64_elf: CommonOptions,
 
+    kvx_lp64: CommonOptions,
+    kvx_ilp32: CommonOptions,
+
     /// The standard `lanai` calling convention.
     lanai_sysv: CommonOptions,
 
@@ -959,6 +962,7 @@ pub const VaList = switch (builtin.cpu.arch) {
     .csky,
     .hppa,
     .hppa64,
+    .kvx,
     .lanai,
     .loongarch32,
     .loongarch64,

src/Sema.zig

@@ -9074,6 +9074,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
     .hexagon_sysv_hvx,
     .hppa_elf,
     .hppa64_elf,
+    .kvx_lp64,
+    .kvx_ilp32,
     .lanai_sysv,
     .loongarch64_lp64,
     .loongarch32_ilp32,

src/codegen/llvm.zig

@@ -111,6 +111,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
         .hppa,
         .hppa64,
         .kalimba,
+        .kvx,
         .microblaze,
         .microblazeel,
         .or1k,
@@ -476,6 +477,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
         .hppa,
         .hppa64,
         .kalimba,
+        .kvx,
         .microblaze,
         .microblazeel,
         .or1k,
@@ -11930,6 +11932,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
         .hexagon_sysv_hvx,
         .hppa_elf,
         .hppa64_elf,
+        .kvx_lp64,
+        .kvx_ilp32,
         .lanai_sysv,
         .loongarch64_lp64,
         .loongarch32_ilp32,
@@ -13113,6 +13117,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
         .hppa,
         .hppa64,
         .kalimba,
+        .kvx,
         .microblaze,
         .microblazeel,
         .or1k,

src/target.zig

@@ -219,6 +219,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
         .hppa,
         .hppa64,
         .kalimba,
+        .kvx,
         .microblaze,
         .microblazeel,
         .or1k,

tools/update_cpu_features.zig

@@ -973,6 +973,43 @@ const targets = [_]ArchTarget{
             .td_name = "Hexagon",
         },
     },
+    .{
+        .zig_name = "kvx",
+        .llvm = null,
+        .extra_features = &.{
+            .{
+                .zig_name = "v3_1",
+                .desc = "Enable ISA v3.1",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "v3_2",
+                .desc = "Enable ISA v3.2",
+                .deps = &.{"v3_1"},
+            },
+            .{
+                .zig_name = "v4_1",
+                .desc = "Enable ISA v4.1",
+                .deps = &.{"v3_2"},
+            },
+        },
+        .extra_cpus = &.{
+            .{
+                .llvm_name = null,
+                .zig_name = "coolidge_v1",
+                .features = &.{
+                    "v3_1",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "coolidge_v2",
+                .features = &.{
+                    "v3_2",
+                },
+            },
+        },
+    },
     .{
         .zig_name = "lanai",
         .llvm = .{