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https://github.com/ziglang/zig.git
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stage2: fix loading pointer value from register
Fix accessing optional payload.
This commit is contained in:
Jakub Konka
parent
b3f70db438
commit
2b77775cbb
@ -1150,17 +1150,10 @@ fn airOptionalPayload(self: *Self, inst: Air.Inst.Index) !void {
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const ty_op = self.air.instructions.items(.data)[inst].ty_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const operand = try self.resolveInst(ty_op.operand);
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const dst_mcv: MCValue = blk: {
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if (self.reuseOperand(inst, ty_op.operand, 0, operand)) {
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break :blk operand;
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} else {
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break :blk try self.allocRegOrMem(inst, true);
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}
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};
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const ty = self.air.typeOf(ty_op.operand);
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var buf: Type.Payload.ElemType = undefined;
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try self.load(dst_mcv, operand, ty.optionalChild(&buf));
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break :result dst_mcv;
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if (self.reuseOperand(inst, ty_op.operand, 0, operand)) {
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break :result operand;
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}
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break :result try self.copyToNewRegister(inst, operand);
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};
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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@ -1471,6 +1464,7 @@ fn reuseOperand(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, op_ind
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fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!void {
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const elem_ty = ptr_ty.elemType();
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const abi_size = elem_ty.abiSize(self.target.*);
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switch (ptr) {
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.none => unreachable,
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.undef => unreachable,
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@ -1478,7 +1472,9 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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.dead => unreachable,
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.compare_flags_unsigned => unreachable,
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.compare_flags_signed => unreachable,
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.immediate => |imm| try self.setRegOrMem(elem_ty, dst_mcv, .{ .memory = imm }),
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.immediate => |imm| {
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try self.setRegOrMem(elem_ty, dst_mcv, .{ .memory = imm });
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},
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.ptr_stack_offset => |off| {
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try self.setRegOrMem(elem_ty, dst_mcv, .{ .stack_offset = off });
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},
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@ -1488,7 +1484,58 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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.embedded_in_code => {
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return self.fail("TODO implement loading from MCValue.embedded_in_code", .{});
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},
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.register => |reg| try self.setRegOrMem(ptr_ty, dst_mcv, .{ .register = reg }),
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.register => |reg| {
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switch (dst_mcv) {
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.dead => unreachable,
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.undef => unreachable,
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.compare_flags_unsigned => unreachable,
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.compare_flags_signed => unreachable,
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.embedded_in_code => unreachable,
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.register => |dst_reg| {
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// mov dst_reg, [reg]
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
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.reg2 = reg,
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.flags = 0b01,
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}).encode(),
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.data = .{ .imm = 0 },
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});
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},
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.stack_offset => |unadjusted_off| {
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if (abi_size <= 8) {
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const tmp_reg = try self.register_manager.allocReg(null, &.{reg});
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try self.load(.{ .register = tmp_reg }, ptr, ptr_ty);
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return self.genSetStack(elem_ty, unadjusted_off, MCValue{ .register = tmp_reg });
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}
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const regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{ reg, .rax, .rcx });
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const addr_reg = regs[0];
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const len_reg = regs[1];
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const off = unadjusted_off + abi_size;
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(addr_reg, @divExact(reg.size(), 8)),
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.reg2 = reg,
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}).encode(),
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.data = undefined,
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});
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// TODO allow for abi size to be u64
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try self.genSetReg(Type.initTag(.u32), len_reg, .{ .immediate = @intCast(u32, abi_size) });
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return self.genInlineMemcpy(
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-@intCast(i32, off),
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registerAlias(addr_reg, @divExact(reg.size(), 8)),
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len_reg.to64(),
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);
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},
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else => return self.fail("TODO implement loading from register into {}", .{dst_mcv}),
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}
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},
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.memory => |addr| {
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const reg = try self.copyToTmpRegister(ptr_ty, .{ .memory = addr });
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try self.load(dst_mcv, .{ .register = reg }, ptr_ty);
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@ -3071,7 +3118,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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return self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
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}
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const regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{});
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const regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{ .rax, .rcx });
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const addr_reg = regs[0];
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const len_reg = regs[1];
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@ -493,13 +493,14 @@ fn mirArithScaleSrc(isel: *Isel, tag: Tag, inst: Mir.Inst.Index) InnerError!void
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const scale = ops.flags;
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const imm = isel.mir.instructions.items(.data)[inst].imm;
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// OP reg1, [reg2 + scale*rcx + imm32]
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const scale_index = ScaleIndex{
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.scale = scale,
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.index = .rcx,
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};
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
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.disp = imm,
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.base = ops.reg2,
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.scale_index = .{
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.scale = scale,
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.index = .rcx,
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},
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.scale_index = scale_index,
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}), isel.code) catch |err| isel.failWithLoweringError(err);
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}
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@ -507,25 +508,23 @@ fn mirArithScaleDst(isel: *Isel, tag: Tag, inst: Mir.Inst.Index) InnerError!void
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const ops = Mir.Ops.decode(isel.mir.instructions.items(.ops)[inst]);
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const scale = ops.flags;
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const imm = isel.mir.instructions.items(.data)[inst].imm;
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const scale_index = ScaleIndex{
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.scale = scale,
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.index = .rax,
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};
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if (ops.reg2 == .none) {
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// OP qword ptr [reg1 + scale*rax + 0], imm32
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return lowerToMiEnc(tag, RegisterOrMemory.mem(.qword_ptr, .{
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.disp = 0,
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.base = ops.reg1,
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.scale_index = .{
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.scale = scale,
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.index = .rax,
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},
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.scale_index = scale_index,
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}), imm, isel.code) catch |err| isel.failWithLoweringError(err);
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}
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// OP [reg1 + scale*rax + imm32], reg2
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return lowerToMrEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg2.size()), .{
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.disp = imm,
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.base = ops.reg1,
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.scale_index = .{
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.scale = scale,
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.index = .rax,
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},
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.scale_index = scale_index,
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}), ops.reg2, isel.code) catch |err| isel.failWithLoweringError(err);
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}
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@ -534,14 +533,15 @@ fn mirArithScaleImm(isel: *Isel, tag: Tag, inst: Mir.Inst.Index) InnerError!void
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const scale = ops.flags;
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const payload = isel.mir.instructions.items(.data)[inst].payload;
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const imm_pair = isel.mir.extraData(Mir.ImmPair, payload).data;
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const scale_index = ScaleIndex{
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.scale = scale,
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.index = .rax,
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};
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// OP qword ptr [reg1 + scale*rax + imm32], imm32
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return lowerToMiEnc(tag, RegisterOrMemory.mem(.qword_ptr, .{
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.disp = imm_pair.dest_off,
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.base = ops.reg1,
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.scale_index = .{
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.scale = scale,
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.index = .rax,
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},
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.scale_index = scale_index,
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}), imm_pair.operand, isel.code) catch |err| isel.failWithLoweringError(err);
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}
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@ -1907,6 +1907,15 @@ test "lower RM encoding" {
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},
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}), isel.code());
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try expectEqualHexStrings("\x48\x8B\x44\xCD\xF8", isel.lowered(), "mov rax, qword ptr [rbp + rcx*8 - 8]");
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try lowerToRmEnc(.mov, .r8b, RegisterOrMemory.mem(.byte_ptr, .{
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.disp = -24,
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.base = .rsi,
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.scale_index = .{
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.scale = 0,
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.index = .rcx,
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},
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}), isel.code());
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try expectEqualHexStrings("\x44\x8A\x44\x0E\xE8", isel.lowered(), "mov r8b, byte ptr [rsi + rcx*1 - 24]");
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}
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test "lower MR encoding" {
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