diff --git a/lib/compiler_rt/udivmodei4.zig b/lib/compiler_rt/udivmodei4.zig
index 52a0c01d6b..6bddd78b81 100644
--- a/lib/compiler_rt/udivmodei4.zig
+++ b/lib/compiler_rt/udivmodei4.zig
@@ -114,17 +114,17 @@ fn divmod(q: ?[]u32, r: ?[]u32, u: []const u32, v: []const u32) !void {
 
 pub fn __udivei4(r_q: [*]u32, u_p: [*]const u32, v_p: [*]const u32, bits: usize) callconv(.C) void {
     @setRuntimeSafety(builtin.is_test);
-    const u = u_p[0 .. bits / 32];
-    const v = v_p[0 .. bits / 32];
-    const q = r_q[0 .. bits / 32];
+    const u = u_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
+    const v = v_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
+    const q = r_q[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
     @call(.always_inline, divmod, .{ q, null, u, v }) catch unreachable;
 }
 
 pub fn __umodei4(r_p: [*]u32, u_p: [*]const u32, v_p: [*]const u32, bits: usize) callconv(.C) void {
     @setRuntimeSafety(builtin.is_test);
-    const u = u_p[0 .. bits / 32];
-    const v = v_p[0 .. bits / 32];
-    const r = r_p[0 .. bits / 32];
+    const u = u_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
+    const v = v_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
+    const r = r_p[0 .. std.math.divCeil(usize, bits, 32) catch unreachable];
     @call(.always_inline, divmod, .{ null, r, u, v }) catch unreachable;
 }
 
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index 12e75a0516..1200dd4d49 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -3030,7 +3030,11 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {
 
             try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});
             break :dst dst_mcv;
-        } else try self.allocRegOrMem(inst, true);
+        } else dst: {
+            const dst_mcv = try self.allocRegOrMem(inst, true);
+            try self.genCopy(dst_ty, dst_mcv, src_mcv, .{});
+            break :dst dst_mcv;
+        };
 
         if (dst_ty.zigTypeTag(mod) == .Vector) {
             assert(src_ty.zigTypeTag(mod) == .Vector and dst_ty.vectorLen(mod) == src_ty.vectorLen(mod));