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Merge pull request #7116 from joachimschmidt557/stage2-arm
stage2 ARM: add basic arithmetic instructions
This commit is contained in:
Andrew Kelley
GitHub
commit
263f25fea6
174
src/codegen.zig
174
src/codegen.zig
@ -975,6 +975,18 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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};
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return try self.genX8664BinMath(&inst.base, inst.operand, &imm.base, 6, 0x30);
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},
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.arm, .armeb => {
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var imm = ir.Inst.Constant{
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.base = .{
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.tag = .constant,
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.deaths = 0,
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.ty = inst.operand.ty,
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.src = inst.operand.src,
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},
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.val = Value.initTag(.bool_true),
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};
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return try self.genArmBinOp(&inst.base, inst.operand, &imm.base, .not);
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},
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else => return self.fail(inst.base.src, "TODO implement NOT for {}", .{self.target.cpu.arch}),
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}
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}
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@ -987,6 +999,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.x86_64 => {
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return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 0, 0x00);
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},
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.arm, .armeb => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .add),
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else => return self.fail(inst.base.src, "TODO implement add for {}", .{self.target.cpu.arch}),
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}
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}
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@ -1144,10 +1157,108 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.x86_64 => {
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return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 5, 0x28);
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},
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.arm, .armeb => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .sub),
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else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}),
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}
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}
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fn genArmBinOp(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, op: ir.Inst.Tag) !MCValue {
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const lhs = try self.resolveInst(op_lhs);
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const rhs = try self.resolveInst(op_rhs);
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// Destination must be a register
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// Source may be register, memory or an immediate
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//
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// So there are two options: (lhs is src and rhs is dest)
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// or (rhs is src and lhs is dest)
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const lhs_is_dest = blk: {
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if (self.reuseOperand(inst, 0, lhs)) {
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break :blk true;
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} else if (self.reuseOperand(inst, 1, rhs)) {
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break :blk false;
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} else {
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break :blk lhs == .register;
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}
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};
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var dst_mcv: MCValue = undefined;
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var src_mcv: MCValue = undefined;
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var src_inst: *ir.Inst = undefined;
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if (lhs_is_dest) {
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// LHS is the destination
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// RHS is the source
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src_inst = op_rhs;
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src_mcv = rhs;
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dst_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs;
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} else {
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// RHS is the destination
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// LHS is the source
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src_inst = op_lhs;
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src_mcv = lhs;
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dst_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs;
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}
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try self.genArmBinOpCode(inst.src, dst_mcv.register, src_mcv, lhs_is_dest, op);
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return dst_mcv;
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}
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fn genArmBinOpCode(
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self: *Self,
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src: usize,
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dst_reg: Register,
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src_mcv: MCValue,
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lhs_is_dest: bool,
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op: ir.Inst.Tag,
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) !void {
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const operand = switch (src_mcv) {
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.none => unreachable,
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.undef => unreachable,
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.dead, .unreach => unreachable,
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.compare_flags_unsigned => unreachable,
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.compare_flags_signed => unreachable,
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.ptr_stack_offset => unreachable,
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.ptr_embedded_in_code => unreachable,
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.immediate => |imm| blk: {
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if (imm > std.math.maxInt(u32)) return self.fail(src, "TODO ARM binary arithmetic immediate larger than u32", .{});
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// Load immediate into register if it doesn't fit
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// as an operand
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break :blk Instruction.Operand.fromU32(@intCast(u32, imm)) orelse
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Instruction.Operand.reg(try self.copyToTmpRegister(src, src_mcv), Instruction.Operand.Shift.none);
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},
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.register => |src_reg| Instruction.Operand.reg(src_reg, Instruction.Operand.Shift.none),
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.stack_offset,
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.embedded_in_code,
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.memory,
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=> Instruction.Operand.reg(try self.copyToTmpRegister(src, src_mcv), Instruction.Operand.Shift.none),
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};
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switch (op) {
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.add => {
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// TODO runtime safety checks (overflow)
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.add(.al, dst_reg, dst_reg, operand).toU32());
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},
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.sub => {
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// TODO runtime safety checks (underflow)
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if (lhs_is_dest) {
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.sub(.al, dst_reg, dst_reg, operand).toU32());
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} else {
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.rsb(.al, dst_reg, dst_reg, operand).toU32());
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}
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},
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.booland => {
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.@"and"(.al, dst_reg, dst_reg, operand).toU32());
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},
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.boolor => {
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, dst_reg, dst_reg, operand).toU32());
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},
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.not => {
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.eor(.al, dst_reg, dst_reg, operand).toU32());
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},
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else => unreachable, // not a binary instruction
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}
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}
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/// ADD, SUB, XOR, OR, AND
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fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue {
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try self.code.ensureCapacity(self.code.items.len + 8);
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@ -2099,14 +2210,19 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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if (inst.base.isUnused())
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return MCValue.dead;
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switch (arch) {
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.x86_64 => if (inst.base.tag == .booland) {
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.x86_64 => switch (inst.base.tag) {
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// lhs AND rhs
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return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 4, 0x20);
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} else {
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.booland => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 4, 0x20),
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// lhs OR rhs
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return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08);
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.boolor => return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08),
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else => unreachable, // Not a boolean operation
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},
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else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}),
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.arm, .armeb => switch (inst.base.tag) {
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.booland => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .booland),
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.boolor => return try self.genArmBinOp(&inst.base, inst.lhs, inst.rhs, .boolor),
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else => unreachable, // Not a boolean operation
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},
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else => return self.fail(inst.base.src, "TODO implement boolean operations for {}", .{self.target.cpu.arch}),
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}
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}
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@ -2359,14 +2475,23 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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return self.fail(src, "TODO implement set stack variable from embedded_in_code", .{});
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},
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.register => |reg| {
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// TODO: strb, strh
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if (stack_offset <= math.maxInt(u12)) {
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.str(.al, reg, .fp, .{
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.offset = Instruction.Offset.imm(@intCast(u12, stack_offset)),
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// TODO: strh
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const offset = if (stack_offset <= math.maxInt(u12)) blk: {
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break :blk Instruction.Offset.imm(@intCast(u12, stack_offset));
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} else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = stack_offset }), 0);
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const abi_size = ty.abiSize(self.target.*);
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switch (abi_size) {
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1 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.strb(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32());
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} else {
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return self.fail(src, "TODO genSetStack with larger offsets", .{});
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}).toU32()),
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2 => return self.fail(src, "TODO implement strh", .{}),
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4 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.str(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32()),
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else => return self.fail(src, "TODO a type of size {} is not allowed in a register", .{abi_size}),
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}
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},
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.memory => |vaddr| {
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@ -2537,15 +2662,26 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, .{ .offset = Instruction.Offset.none }).toU32());
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},
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.stack_offset => |unadjusted_off| {
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// TODO: ldrb, ldrh
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// TODO: ldrh
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// TODO: maybe addressing from sp instead of fp
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if (unadjusted_off <= math.maxInt(u12)) {
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, .fp, .{
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.offset = Instruction.Offset.imm(@intCast(u12, unadjusted_off)),
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const offset = if (unadjusted_off <= math.maxInt(u12)) blk: {
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break :blk Instruction.Offset.imm(@intCast(u12, unadjusted_off));
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} else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = unadjusted_off }), 0);
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// TODO: supply type information to genSetReg as we do to genSetStack
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// const abi_size = ty.abiSize(self.target.*);
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const abi_size = 4;
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switch (abi_size) {
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1 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldrb(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32());
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} else {
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return self.fail(src, "TODO genSetReg with larger stack offset", .{});
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}).toU32()),
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2 => return self.fail(src, "TODO implement strh", .{}),
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4 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32()),
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else => return self.fail(src, "TODO a type of size {} is not allowed in a register", .{abi_size}),
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}
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},
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else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}),
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@ -113,4 +113,40 @@ pub fn addCases(ctx: *TestContext) !void {
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"",
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);
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}
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{
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var case = ctx.exe("addition", linux_arm);
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// Add two numbers
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case.addCompareOutput(
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\\export fn _start() noreturn {
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\\ print(2, 4);
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\\ print(1, 7);
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\\ exit();
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\\}
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\\
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\\fn print(a: u32, b: u32) void {
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\\ asm volatile ("svc #0"
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\\ :
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\\ : [number] "{r7}" (4),
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\\ [arg3] "{r2}" (a + b),
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\\ [arg1] "{r0}" (1),
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\\ [arg2] "{r1}" (@ptrToInt("123456789"))
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\\ : "memory"
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\\ );
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\\ return;
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\\}
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\\
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\\fn exit() noreturn {
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\\ asm volatile ("svc #0"
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\\ :
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\\ : [number] "{r7}" (1),
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\\ [arg1] "{r0}" (0)
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\\ : "memory"
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\\ );
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\\ unreachable;
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\\}
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,
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"12345612345678",
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);
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}
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}
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