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x86_64: hack around silent f80 miscompilations
The x87 kind sucks.
This commit is contained in:
Jacob Young
parent
b19fd485b1
commit
24c67992e0
@ -5263,21 +5263,29 @@ fn airRound(self: *Self, inst: Air.Inst.Index, mode: RoundMode) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const ty = self.typeOf(un_op);
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const src_mcv = try self.resolveInst(un_op);
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const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
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src_mcv
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else
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try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
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const dst_reg = dst_mcv.getReg().?;
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const dst_lock = self.register_manager.lockReg(dst_reg);
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defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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try self.genRound(ty, dst_reg, src_mcv, mode);
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return self.finishAir(inst, dst_mcv, .{ un_op, .none, .none });
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const result = result: {
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switch (try self.genRoundLibcall(ty, .{ .air_ref = un_op }, mode)) {
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.none => {},
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else => |dst_mcv| break :result dst_mcv,
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}
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const src_mcv = try self.resolveInst(un_op);
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const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, un_op, 0, src_mcv))
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src_mcv
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else
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try self.copyToRegisterWithInstTracking(inst, ty, src_mcv);
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const dst_reg = dst_mcv.getReg().?;
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const dst_lock = self.register_manager.lockReg(dst_reg);
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defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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try self.genRound(ty, dst_reg, src_mcv, mode);
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break :result dst_mcv;
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};
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return self.finishAir(inst, result, .{ un_op, .none, .none });
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}
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fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: RoundMode) !void {
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fn getRoundTag(self: *Self, ty: Type) ?Mir.Inst.FixedTag {
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const mod = self.bin_file.options.module.?;
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const mir_tag = @as(?Mir.Inst.FixedTag, if (self.hasFeature(.sse4_1)) switch (ty.zigTypeTag(mod)) {
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return if (self.hasFeature(.sse4_1)) switch (ty.zigTypeTag(mod)) {
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.Float => switch (ty.floatBits(self.target.*)) {
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32 => if (self.hasFeature(.avx)) .{ .v_ss, .round } else .{ ._ss, .round },
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64 => if (self.hasFeature(.avx)) .{ .v_sd, .round } else .{ ._sd, .round },
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@ -5304,26 +5312,38 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: Ro
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else => null,
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},
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else => unreachable,
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} else null) orelse {
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if (ty.zigTypeTag(mod) != .Float)
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return self.fail("TODO implement genRound for {}", .{ty.fmt(mod)});
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} else null;
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}
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var callee: ["__trunc?".len]u8 = undefined;
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const res = try self.genCall(.{ .lib = .{
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.return_type = ty.toIntern(),
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.param_types = &.{ty.toIntern()},
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.callee = std.fmt.bufPrint(&callee, "{s}{s}{s}", .{
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floatLibcAbiPrefix(ty),
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switch (mode.mode) {
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.down => "floor",
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.up => "ceil",
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.zero => "trunc",
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else => unreachable,
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},
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floatLibcAbiSuffix(ty),
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}) catch unreachable,
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} }, &.{ty}, &.{src_mcv});
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return self.genSetReg(dst_reg, ty, res);
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fn genRoundLibcall(self: *Self, ty: Type, src_mcv: MCValue, mode: RoundMode) !MCValue {
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const mod = self.bin_file.options.module.?;
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if (self.getRoundTag(ty)) |_| return .none;
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if (ty.zigTypeTag(mod) != .Float)
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return self.fail("TODO implement genRound for {}", .{ty.fmt(mod)});
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var callee: ["__trunc?".len]u8 = undefined;
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return try self.genCall(.{ .lib = .{
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.return_type = ty.toIntern(),
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.param_types = &.{ty.toIntern()},
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.callee = std.fmt.bufPrint(&callee, "{s}{s}{s}", .{
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floatLibcAbiPrefix(ty),
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switch (mode.mode) {
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.down => "floor",
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.up => "ceil",
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.zero => "trunc",
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else => unreachable,
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},
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floatLibcAbiSuffix(ty),
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}) catch unreachable,
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} }, &.{ty}, &.{src_mcv});
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}
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fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: RoundMode) !void {
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const mod = self.bin_file.options.module.?;
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const mir_tag = self.getRoundTag(ty) orelse {
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const result = try self.genRoundLibcall(ty, src_mcv, mode);
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return self.genSetReg(dst_reg, ty, result);
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};
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const abi_size: u32 = @intCast(ty.abiSize(mod));
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const dst_alias = registerAlias(dst_reg, abi_size);
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@ -6760,11 +6780,17 @@ fn genBinOp(
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else => unreachable,
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}) {
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var callee: ["__add?f3".len]u8 = undefined;
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return self.genCall(.{ .lib = .{
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const result = try self.genCall(.{ .lib = .{
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.return_type = lhs_ty.toIntern(),
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.param_types = &.{ lhs_ty.toIntern(), rhs_ty.toIntern() },
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.callee = switch (air_tag) {
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.add, .sub, .mul, .div_float => std.fmt.bufPrint(&callee, "__{s}{c}f3", .{
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.add,
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.sub,
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.mul,
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.div_float,
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.div_trunc,
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.div_floor,
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=> std.fmt.bufPrint(&callee, "__{s}{c}f3", .{
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@tagName(air_tag)[0..3],
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floatCompilerRtAbiName(lhs_ty.floatBits(self.target.*)),
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}),
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@ -6778,6 +6804,17 @@ fn genBinOp(
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}),
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} catch unreachable,
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} }, &.{ lhs_ty, rhs_ty }, &.{ .{ .air_ref = lhs_air }, .{ .air_ref = rhs_air } });
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return switch (air_tag) {
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.div_trunc, .div_floor => try self.genRoundLibcall(lhs_ty, result, .{
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.mode = switch (air_tag) {
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.div_trunc => .zero,
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.div_floor => .down,
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else => unreachable,
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},
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.precision = .inexact,
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}),
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else => result,
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};
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}
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if ((lhs_ty.scalarType(mod).isRuntimeFloat() and
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@ -7666,16 +7703,14 @@ fn genBinOp(
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switch (air_tag) {
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.add, .add_wrap, .sub, .sub_wrap, .mul, .mul_wrap, .div_float, .div_exact => {},
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.div_trunc, .div_floor => try self.genRound(
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lhs_ty,
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dst_reg,
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.{ .register = dst_reg },
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.{ .mode = switch (air_tag) {
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.div_trunc, .div_floor => try self.genRound(lhs_ty, dst_reg, .{ .register = dst_reg }, .{
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.mode = switch (air_tag) {
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.div_trunc => .zero,
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.div_floor => .down,
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else => unreachable,
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}, .precision = .inexact },
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),
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},
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.precision = .inexact,
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}),
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.bit_and, .bit_or, .xor => {},
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.max, .min => if (maybe_mask_reg) |mask_reg| if (self.hasFeature(.avx)) {
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const rhs_copy_reg = registerAlias(src_mcv.getReg().?, abi_size);
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@ -8673,7 +8708,10 @@ fn genCall(self: *Self, info: union(enum) {
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try self.spillRegisters(®s);
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try arg_locks.appendSlice(&self.register_manager.lockRegs(2, regs));
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},
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.load_frame => try self.genCopy(arg_ty, dst_arg, src_arg),
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.load_frame => {
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try self.genCopy(arg_ty, dst_arg, src_arg);
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try self.freeValue(src_arg);
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},
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else => unreachable,
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};
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@ -1029,7 +1029,7 @@ test "@floor f80/f128/c_longdouble" {
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_c and builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.os.tag == .windows) {
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// https://github.com/ziglang/zig/issues/12602
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@ -1111,7 +1111,7 @@ test "@ceil f80/f128/c_longdouble" {
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_c and builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.os.tag == .windows) {
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// https://github.com/ziglang/zig/issues/12602
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@ -1203,7 +1203,7 @@ test "@trunc f80/f128/c_longdouble" {
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_c and builtin.cpu.arch.isArmOrThumb()) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.os.tag == .windows) {
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// https://github.com/ziglang/zig/issues/12602
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