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https://github.com/ziglang/zig.git
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x64: make one entry point for binary ops
* rename `genBinMathOp` into `genBinOp` and handle commutativity * rename `genBinMathOpMir` into `genBinOpMir`
This commit is contained in:
Jakub Konka
parent
9c3d24ea0b
commit
20e7f1218b
@ -586,11 +586,11 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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switch (air_tags[inst]) {
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// zig fmt: off
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.add => try self.airAdd(inst),
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.addwrap => try self.airAdd(inst),
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.add => try self.airBinOp(inst),
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.addwrap => try self.airBinOp(inst),
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.add_sat => try self.airAddSat(inst),
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.sub => try self.airSub(inst),
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.subwrap => try self.airSub(inst),
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.sub => try self.airBinOp(inst),
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.subwrap => try self.airBinOp(inst),
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.sub_sat => try self.airSubSat(inst),
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.mul => try self.airMul(inst),
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.mulwrap => try self.airMul(inst),
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@ -601,8 +601,8 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.shl_sat => try self.airShlSat(inst),
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.min => try self.airMin(inst),
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.max => try self.airMax(inst),
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.ptr_add => try self.airPtrAdd(inst),
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.ptr_sub => try self.airPtrSub(inst),
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.ptr_add => try self.airBinOp(inst),
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.ptr_sub => try self.airBinOp(inst),
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.slice => try self.airSlice(inst),
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.sqrt,
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@ -638,11 +638,11 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.cmp_vector => try self.airCmpVector(inst),
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.cmp_lt_errors_len => try self.airCmpLtErrorsLen(inst),
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.bool_and => try self.airBoolOp(inst),
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.bool_or => try self.airBoolOp(inst),
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.bit_and => try self.airBitAnd(inst),
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.bit_or => try self.airBitOr(inst),
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.xor => try self.airXor(inst),
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.bool_and => try self.airBinOp(inst),
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.bool_or => try self.airBinOp(inst),
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.bit_and => try self.airBinOp(inst),
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.bit_or => try self.airBinOp(inst),
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.xor => try self.airBinOp(inst),
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.shr, .shr_exact => try self.airShr(inst),
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.alloc => try self.airAlloc(inst),
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@ -1122,7 +1122,7 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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},
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else => {},
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}
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break :result try self.genBinMathOp(inst, ty_op.operand, .bool_true);
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break :result try self.genBinOp(inst, ty_op.operand, .bool_true);
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};
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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@ -1159,7 +1159,7 @@ fn airMin(self: *Self, inst: Air.Inst.Index) !void {
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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try self.genBinMathOpMir(.cmp, ty, .{ .register = lhs_reg }, rhs_mcv);
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try self.genBinOpMir(.cmp, ty, .{ .register = lhs_reg }, rhs_mcv);
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const dst_mcv = try self.copyToRegisterWithInstTracking(inst, ty, rhs_mcv);
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_ = try self.addInst(.{
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@ -1185,63 +1185,12 @@ fn airMax(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn genPtrBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air.Inst.Ref) !MCValue {
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const dst_ty = self.air.typeOfIndex(inst);
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const elem_size = dst_ty.elemType2().abiSize(self.target.*);
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const ptr = try self.resolveInst(op_lhs);
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const offset = try self.resolveInst(op_rhs);
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const offset_ty = self.air.typeOf(op_rhs);
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const offset_lock: ?RegisterLock = switch (offset) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (offset_lock) |lock| self.register_manager.unlockReg(lock);
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const dst_mcv: MCValue = blk: {
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if (self.reuseOperand(inst, op_lhs, 0, ptr)) {
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if (ptr.isMemory() or ptr.isRegister()) break :blk ptr;
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}
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break :blk MCValue{ .register = try self.copyToTmpRegister(dst_ty, ptr) };
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};
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const dst_mcv_lock: ?RegisterLock = switch (dst_mcv) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (dst_mcv_lock) |lock| self.register_manager.unlockReg(lock);
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const offset_mcv: MCValue = blk: {
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if (self.reuseOperand(inst, op_rhs, 1, offset)) {
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if (offset.isRegister()) break :blk offset;
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}
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break :blk MCValue{ .register = try self.copyToTmpRegister(offset_ty, offset) };
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};
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const offset_mcv_lock: ?RegisterLock = switch (offset_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (offset_mcv_lock) |lock| self.register_manager.unlockReg(lock);
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try self.genIntMulComplexOpMir(offset_ty, offset_mcv, .{ .immediate = elem_size });
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const tag = self.air.instructions.items(.tag)[inst];
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switch (tag) {
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.ptr_add => try self.genBinMathOpMir(.add, dst_ty, dst_mcv, offset_mcv),
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.ptr_sub => try self.genBinMathOpMir(.sub, dst_ty, dst_mcv, offset_mcv),
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else => unreachable,
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}
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return dst_mcv;
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}
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fn airPtrAdd(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.genPtrBinMathOp(inst, bin_op.lhs, bin_op.rhs);
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try self.genBinOp(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1250,7 +1199,7 @@ fn airPtrSub(self: *Self, inst: Air.Inst.Index) !void {
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const result = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.genPtrBinMathOp(inst, bin_op.lhs, bin_op.rhs);
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try self.genBinOp(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1275,21 +1224,12 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airAdd(self: *Self, inst: Air.Inst.Index) !void {
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fn airBinOp(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airAddWrap(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs);
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try self.genBinOp(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1302,60 +1242,6 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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/// Result is always a register.
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fn genSubOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air.Inst.Ref) !MCValue {
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const dst_ty = self.air.typeOf(op_lhs);
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const lhs = try self.resolveInst(op_lhs);
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const lhs_lock: ?RegisterLock = switch (lhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs = try self.resolveInst(op_rhs);
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const rhs_lock: ?RegisterLock = switch (rhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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const dst_mcv: MCValue = blk: {
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if (self.reuseOperand(inst, op_lhs, 0, lhs) and lhs.isRegister()) {
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break :blk lhs;
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}
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break :blk try self.copyToRegisterWithInstTracking(inst, dst_ty, lhs);
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};
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const dst_mcv_lock: ?RegisterLock = switch (dst_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (dst_mcv_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs_mcv: MCValue = blk: {
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if (rhs.isMemory() or rhs.isRegister()) break :blk rhs;
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break :blk MCValue{ .register = try self.copyToTmpRegister(dst_ty, rhs) };
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};
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const rhs_mcv_lock: ?RegisterLock = switch (rhs_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (rhs_mcv_lock) |lock| self.register_manager.unlockReg(lock);
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try self.genBinMathOpMir(.sub, dst_ty, dst_mcv, rhs_mcv);
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return dst_mcv;
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}
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fn airSub(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.genSubOp(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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@ -1422,7 +1308,7 @@ fn airAddWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = inst;
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const partial = try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs);
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const partial = try self.genBinOp(inst, bin_op.lhs, bin_op.rhs);
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const result: MCValue = switch (int_info.signedness) {
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.signed => .{ .register_overflow_signed = partial.register },
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.unsigned => .{ .register_overflow_unsigned = partial.register },
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@ -1454,7 +1340,7 @@ fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = inst;
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const partial = try self.genSubOp(inst, bin_op.lhs, bin_op.rhs);
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const partial = try self.genBinOp(inst, bin_op.lhs, bin_op.rhs);
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const result: MCValue = switch (int_info.signedness) {
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.signed => .{ .register_overflow_signed = partial.register },
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.unsigned => .{ .register_overflow_unsigned = partial.register },
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@ -1605,7 +1491,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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const scratch_reg = temp_regs[1];
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try self.genSetReg(extended_ty, scratch_reg, .{ .register = dst_reg });
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try self.truncateRegister(ty, scratch_reg);
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try self.genBinMathOpMir(
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try self.genBinOpMir(
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.cmp,
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extended_ty,
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.{ .register = dst_reg },
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@ -1622,7 +1508,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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.data = undefined,
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});
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try self.genBinMathOpMir(
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try self.genBinOpMir(
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.@"or",
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Type.u8,
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.{ .register = overflow_reg },
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@ -1781,7 +1667,7 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa
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}).encode(),
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.data = undefined,
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});
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try self.genBinMathOpMir(.add, Type.isize, .{ .register = divisor }, .{ .register = .rax });
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try self.genBinOpMir(.add, Type.isize, .{ .register = divisor }, .{ .register = .rax });
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return MCValue{ .register = divisor };
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}
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@ -1945,7 +1831,7 @@ fn airMod(self: *Self, inst: Air.Inst.Index) !void {
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try self.genIntMulComplexOpMir(ty, div_floor, rhs);
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const result = try self.copyToRegisterWithInstTracking(inst, ty, lhs);
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try self.genBinMathOpMir(.sub, ty, result, div_floor);
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try self.genBinOpMir(.sub, ty, result, div_floor);
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break :result result;
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},
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@ -1955,33 +1841,6 @@ fn airMod(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airBitAnd(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airBitOr(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airXor(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airShl(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (self.liveness.isUnused(inst)) {
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@ -1989,6 +1848,7 @@ fn airShl(self: *Self, inst: Air.Inst.Index) !void {
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}
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const ty = self.air.typeOfIndex(inst);
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const tag = self.air.instructions.items(.tag)[inst];
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switch (tag) {
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.shl_exact => return self.fail("TODO implement {} for type {}", .{ tag, ty.fmtDebug() }),
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@ -2470,7 +2330,7 @@ fn genSliceElemPtr(self: *Self, lhs: Air.Inst.Ref, rhs: Air.Inst.Ref) !MCValue {
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}
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// TODO we could allocate register here, but need to expect addr register and potentially
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// offset register.
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try self.genBinMathOpMir(.add, slice_ptr_field_type, .{ .register = addr_reg }, .{
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try self.genBinOpMir(.add, slice_ptr_field_type, .{ .register = addr_reg }, .{
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.register = offset_reg,
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});
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return MCValue{ .register = addr_reg.to64() };
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@ -2573,7 +2433,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
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// TODO we could allocate register here, but need to expect addr register and potentially
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// offset register.
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const dst_mcv = try self.allocRegOrMem(inst, false);
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try self.genBinMathOpMir(.add, Type.usize, .{ .register = addr_reg }, .{ .register = offset_reg });
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try self.genBinOpMir(.add, Type.usize, .{ .register = addr_reg }, .{ .register = offset_reg });
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try self.load(dst_mcv, .{ .register = addr_reg.to64() }, array_ty);
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return self.finishAir(inst, dst_mcv, .{ bin_op.lhs, bin_op.rhs, .none });
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@ -2613,7 +2473,7 @@ fn airPtrElemVal(self: *Self, inst: Air.Inst.Index) !void {
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defer self.register_manager.unlockReg(offset_reg_lock);
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const dst_mcv = try self.copyToRegisterWithInstTracking(inst, ptr_ty, ptr);
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try self.genBinMathOpMir(.add, ptr_ty, dst_mcv, .{ .register = offset_reg });
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try self.genBinOpMir(.add, ptr_ty, dst_mcv, .{ .register = offset_reg });
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const result: MCValue = result: {
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if (elem_abi_size > 8) {
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@ -2667,7 +2527,7 @@ fn airPtrElemPtr(self: *Self, inst: Air.Inst.Index) !void {
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defer self.register_manager.unlockReg(offset_reg_lock);
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const dst_mcv = try self.copyToRegisterWithInstTracking(inst, ptr_ty, ptr);
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try self.genBinMathOpMir(.add, ptr_ty, dst_mcv, .{ .register = offset_reg });
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try self.genBinOpMir(.add, ptr_ty, dst_mcv, .{ .register = offset_reg });
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return self.finishAir(inst, dst_mcv, .{ extra.lhs, extra.rhs, .none });
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}
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@ -2700,7 +2560,7 @@ fn airSetUnionTag(self: *Self, inst: Air.Inst.Index) !void {
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const adjusted_ptr: MCValue = if (layout.payload_size > 0 and layout.tag_align < layout.payload_align) blk: {
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// TODO reusing the operand
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const reg = try self.copyToTmpRegister(ptr_ty, ptr);
|
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try self.genBinMathOpMir(.add, ptr_ty, .{ .register = reg }, .{ .immediate = layout.payload_size });
|
||||
try self.genBinOpMir(.add, ptr_ty, .{ .register = reg }, .{ .immediate = layout.payload_size });
|
||||
break :blk MCValue{ .register = reg };
|
||||
} else ptr;
|
||||
|
||||
@ -3267,7 +3127,7 @@ fn structFieldPtr(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, inde
|
||||
defer self.register_manager.unlockReg(offset_reg_lock);
|
||||
|
||||
const dst_mcv = try self.copyToRegisterWithInstTracking(inst, ptr_ty, mcv);
|
||||
try self.genBinMathOpMir(.add, ptr_ty, dst_mcv, .{ .register = offset_reg });
|
||||
try self.genBinOpMir(.add, ptr_ty, dst_mcv, .{ .register = offset_reg });
|
||||
break :result dst_mcv;
|
||||
},
|
||||
.ptr_stack_offset => |off| {
|
||||
@ -3297,7 +3157,7 @@ fn structFieldPtr(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, inde
|
||||
const result_reg_lock = self.register_manager.lockReg(result_reg);
|
||||
defer if (result_reg_lock) |lock| self.register_manager.unlockReg(lock);
|
||||
|
||||
try self.genBinMathOpMir(.add, ptr_ty, .{ .register = result_reg }, .{ .register = offset_reg });
|
||||
try self.genBinOpMir(.add, ptr_ty, .{ .register = result_reg }, .{ .register = offset_reg });
|
||||
break :result MCValue{ .register = result_reg };
|
||||
},
|
||||
else => return self.fail("TODO implement codegen struct_field_ptr for {}", .{mcv}),
|
||||
@ -3357,7 +3217,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
|
||||
const mask = (~@as(u64, 0)) >> mask_shift;
|
||||
|
||||
const tmp_reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = mask });
|
||||
try self.genBinMathOpMir(.@"and", Type.usize, dst_mcv, .{ .register = tmp_reg });
|
||||
try self.genBinOpMir(.@"and", Type.usize, dst_mcv, .{ .register = tmp_reg });
|
||||
|
||||
const signedness: std.builtin.Signedness = blk: {
|
||||
if (struct_field_ty.zigTypeTag() != .Int) break :blk .unsigned;
|
||||
@ -3426,8 +3286,39 @@ fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {
|
||||
}
|
||||
|
||||
/// Result is always a register.
|
||||
fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air.Inst.Ref) !MCValue {
|
||||
fn genBinOp(
|
||||
self: *Self,
|
||||
inst: Air.Inst.Index,
|
||||
op_lhs: Air.Inst.Ref,
|
||||
op_rhs: Air.Inst.Ref,
|
||||
) !MCValue {
|
||||
const tag = self.air.instructions.items(.tag)[inst];
|
||||
const is_commutative: bool = switch (tag) {
|
||||
.add,
|
||||
.addwrap,
|
||||
.add_with_overflow,
|
||||
.bool_or,
|
||||
.bit_or,
|
||||
.bool_and,
|
||||
.bit_and,
|
||||
.xor,
|
||||
.not,
|
||||
=> true,
|
||||
|
||||
.sub,
|
||||
.subwrap,
|
||||
.sub_with_overflow,
|
||||
.mul,
|
||||
.shl,
|
||||
.shr,
|
||||
.ptr_add,
|
||||
.ptr_sub,
|
||||
=> false,
|
||||
|
||||
else => unreachable,
|
||||
};
|
||||
const dst_ty = self.air.typeOf(op_lhs);
|
||||
const src_ty = self.air.typeOf(op_rhs);
|
||||
|
||||
const lhs = try self.resolveInst(op_lhs);
|
||||
const lhs_lock: ?RegisterLock = switch (lhs) {
|
||||
@ -3448,7 +3339,7 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
|
||||
if (self.reuseOperand(inst, op_lhs, 0, lhs) and lhs.isRegister()) {
|
||||
break :blk lhs;
|
||||
}
|
||||
if (self.reuseOperand(inst, op_rhs, 1, rhs) and rhs.isRegister()) {
|
||||
if (is_commutative and self.reuseOperand(inst, op_rhs, 1, rhs) and rhs.isRegister()) {
|
||||
flipped = true;
|
||||
break :blk rhs;
|
||||
}
|
||||
@ -3463,7 +3354,7 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
|
||||
const src_mcv: MCValue = blk: {
|
||||
const mcv = if (flipped) lhs else rhs;
|
||||
if (mcv.isRegister() or mcv.isMemory()) break :blk mcv;
|
||||
break :blk MCValue{ .register = try self.copyToTmpRegister(dst_ty, mcv) };
|
||||
break :blk MCValue{ .register = try self.copyToTmpRegister(src_ty, mcv) };
|
||||
};
|
||||
const src_mcv_lock: ?RegisterLock = switch (src_mcv) {
|
||||
.register => |reg| self.register_manager.lockReg(reg),
|
||||
@ -3471,18 +3362,39 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
|
||||
};
|
||||
defer if (src_mcv_lock) |lock| self.register_manager.unlockReg(lock);
|
||||
|
||||
const tag = self.air.instructions.items(.tag)[inst];
|
||||
switch (tag) {
|
||||
.add, .addwrap, .add_with_overflow => try self.genBinMathOpMir(.add, dst_ty, dst_mcv, src_mcv),
|
||||
.bool_or, .bit_or => try self.genBinMathOpMir(.@"or", dst_ty, dst_mcv, src_mcv),
|
||||
.bool_and, .bit_and => try self.genBinMathOpMir(.@"and", dst_ty, dst_mcv, src_mcv),
|
||||
.xor, .not => try self.genBinMathOpMir(.xor, dst_ty, dst_mcv, src_mcv),
|
||||
.add,
|
||||
.addwrap,
|
||||
.add_with_overflow,
|
||||
=> try self.genBinOpMir(.add, dst_ty, dst_mcv, src_mcv),
|
||||
|
||||
.sub,
|
||||
.subwrap,
|
||||
.sub_with_overflow,
|
||||
=> try self.genBinOpMir(.sub, dst_ty, dst_mcv, src_mcv),
|
||||
|
||||
.ptr_add,
|
||||
.ptr_sub,
|
||||
=> {
|
||||
const mir_tag: Mir.Inst.Tag = switch (tag) {
|
||||
.ptr_add => .add,
|
||||
.ptr_sub => .sub,
|
||||
else => unreachable,
|
||||
};
|
||||
const elem_size = dst_ty.elemType2().abiSize(self.target.*);
|
||||
try self.genIntMulComplexOpMir(src_ty, src_mcv, .{ .immediate = elem_size });
|
||||
try self.genBinOpMir(mir_tag, dst_ty, dst_mcv, src_mcv);
|
||||
},
|
||||
|
||||
.bool_or, .bit_or => try self.genBinOpMir(.@"or", dst_ty, dst_mcv, src_mcv),
|
||||
.bool_and, .bit_and => try self.genBinOpMir(.@"and", dst_ty, dst_mcv, src_mcv),
|
||||
.xor, .not => try self.genBinOpMir(.xor, dst_ty, dst_mcv, src_mcv),
|
||||
else => unreachable,
|
||||
}
|
||||
return dst_mcv;
|
||||
}
|
||||
|
||||
fn genBinMathOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
|
||||
fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
|
||||
const abi_size = @intCast(u32, dst_ty.abiSize(self.target.*));
|
||||
switch (dst_mcv) {
|
||||
.none => unreachable,
|
||||
@ -3504,7 +3416,7 @@ fn genBinMathOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MC
|
||||
defer if (dst_reg_lock) |lock| self.register_manager.unlockReg(lock);
|
||||
|
||||
const reg = try self.copyToTmpRegister(dst_ty, src_mcv);
|
||||
return self.genBinMathOpMir(mir_tag, dst_ty, dst_mcv, .{ .register = reg });
|
||||
return self.genBinOpMir(mir_tag, dst_ty, dst_mcv, .{ .register = reg });
|
||||
},
|
||||
.register => |src_reg| {
|
||||
_ = try self.addInst(.{
|
||||
@ -3536,7 +3448,7 @@ fn genBinMathOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MC
|
||||
defer if (dst_reg_lock) |lock| self.register_manager.unlockReg(lock);
|
||||
|
||||
const reg = try self.copyToTmpRegister(dst_ty, src_mcv);
|
||||
return self.genBinMathOpMir(mir_tag, dst_ty, dst_mcv, .{ .register = reg });
|
||||
return self.genBinOpMir(mir_tag, dst_ty, dst_mcv, .{ .register = reg });
|
||||
},
|
||||
.stack_offset => |off| {
|
||||
if (off > math.maxInt(i32)) {
|
||||
@ -3637,7 +3549,7 @@ fn genBinMathOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MC
|
||||
|
||||
/// Performs multi-operand integer multiplication between dst_mcv and src_mcv, storing the result in dst_mcv.
|
||||
/// Does not support byte-size operands.
|
||||
fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
|
||||
fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) InnerError!void {
|
||||
const abi_size = @intCast(u32, dst_ty.abiSize(self.target.*));
|
||||
switch (dst_mcv) {
|
||||
.none => unreachable,
|
||||
@ -3733,11 +3645,17 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
|
||||
.data = undefined,
|
||||
});
|
||||
// copy dst_reg back out
|
||||
return self.genSetStack(dst_ty, off, MCValue{ .register = dst_reg }, .{});
|
||||
return self.genSetStack(dst_ty, off, .{ .register = dst_reg }, .{});
|
||||
},
|
||||
.immediate => |imm| {
|
||||
_ = imm;
|
||||
return self.fail("TODO implement x86 multiply source immediate", .{});
|
||||
.immediate => {
|
||||
// copy dst to a register
|
||||
const dst_reg = try self.copyToTmpRegister(dst_ty, dst_mcv);
|
||||
const dst_reg_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
|
||||
defer self.register_manager.unlockReg(dst_reg_lock);
|
||||
|
||||
try self.genIntMulComplexOpMir(dst_ty, .{ .register = dst_reg }, src_mcv);
|
||||
|
||||
return self.genSetStack(dst_ty, off, .{ .register = dst_reg }, .{});
|
||||
},
|
||||
.memory, .stack_offset => {
|
||||
return self.fail("TODO implement x86 multiply source memory", .{});
|
||||
@ -4213,7 +4131,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
|
||||
// This instruction supports only signed 32-bit immediates at most.
|
||||
const src_mcv = try self.limitImmediateType(bin_op.rhs, i32);
|
||||
|
||||
try self.genBinMathOpMir(.cmp, ty, dst_mcv, src_mcv);
|
||||
try self.genBinOpMir(.cmp, ty, dst_mcv, src_mcv);
|
||||
break :result switch (signedness) {
|
||||
.signed => MCValue{ .compare_flags_signed = op },
|
||||
.unsigned => MCValue{ .compare_flags_unsigned = op },
|
||||
@ -4606,7 +4524,7 @@ fn isNull(self: *Self, inst: Air.Inst.Index, ty: Type, operand: MCValue) !MCValu
|
||||
break :blk if (payload_ty.hasRuntimeBits()) Type.bool else ty;
|
||||
} else ty;
|
||||
|
||||
try self.genBinMathOpMir(.cmp, cmp_ty, operand, MCValue{ .immediate = 0 });
|
||||
try self.genBinOpMir(.cmp, cmp_ty, operand, MCValue{ .immediate = 0 });
|
||||
|
||||
return MCValue{ .compare_flags_unsigned = .eq };
|
||||
}
|
||||
@ -4629,13 +4547,13 @@ fn isErr(self: *Self, inst: Air.Inst.Index, ty: Type, operand: MCValue) !MCValue
|
||||
|
||||
if (!payload_type.hasRuntimeBits()) {
|
||||
if (err_type.abiSize(self.target.*) <= 8) {
|
||||
try self.genBinMathOpMir(.cmp, err_type, operand, MCValue{ .immediate = 0 });
|
||||
try self.genBinOpMir(.cmp, err_type, operand, MCValue{ .immediate = 0 });
|
||||
return MCValue{ .compare_flags_unsigned = .gt };
|
||||
} else {
|
||||
return self.fail("TODO isErr for errors with size larger than register size", .{});
|
||||
}
|
||||
} else {
|
||||
try self.genBinMathOpMir(.cmp, err_type, operand, MCValue{ .immediate = 0 });
|
||||
try self.genBinOpMir(.cmp, err_type, operand, MCValue{ .immediate = 0 });
|
||||
return MCValue{ .compare_flags_unsigned = .gt };
|
||||
}
|
||||
}
|
||||
@ -5053,21 +4971,6 @@ fn airBr(self: *Self, inst: Air.Inst.Index) !void {
|
||||
return self.finishAir(inst, .dead, .{ branch.operand, .none, .none });
|
||||
}
|
||||
|
||||
fn airBoolOp(self: *Self, inst: Air.Inst.Index) !void {
|
||||
const bin_op = self.air.instructions.items(.data)[inst].bin_op;
|
||||
const air_tags = self.air.instructions.items(.tag);
|
||||
const result: MCValue = if (self.liveness.isUnused(inst))
|
||||
.dead
|
||||
else switch (air_tags[inst]) {
|
||||
// lhs AND rhs
|
||||
.bool_and => try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs),
|
||||
// lhs OR rhs
|
||||
.bool_or => try self.genBinMathOp(inst, bin_op.lhs, bin_op.rhs),
|
||||
else => unreachable, // Not a boolean operation
|
||||
};
|
||||
return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
|
||||
}
|
||||
|
||||
fn br(self: *Self, block: Air.Inst.Index, operand: Air.Inst.Ref) !void {
|
||||
const block_data = self.blocks.getPtr(block).?;
|
||||
|
||||
@ -5844,7 +5747,7 @@ fn genInlineMemset(
|
||||
defer self.register_manager.unlockReg(addr_reg_lock);
|
||||
|
||||
try self.genSetReg(Type.usize, .rax, len);
|
||||
try self.genBinMathOpMir(.sub, Type.usize, .{ .register = .rax }, .{ .immediate = 1 });
|
||||
try self.genBinOpMir(.sub, Type.usize, .{ .register = .rax }, .{ .immediate = 1 });
|
||||
|
||||
// loop:
|
||||
// cmp rax, -1
|
||||
@ -6963,10 +6866,10 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
|
||||
const shift = @intCast(u6, max_reg_bit_width - int_info.bits);
|
||||
const mask = (~@as(u64, 0)) >> shift;
|
||||
if (int_info.bits <= 32) {
|
||||
try self.genBinMathOpMir(.@"and", Type.usize, .{ .register = reg }, .{ .immediate = mask });
|
||||
try self.genBinOpMir(.@"and", Type.usize, .{ .register = reg }, .{ .immediate = mask });
|
||||
} else {
|
||||
const tmp_reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = mask });
|
||||
try self.genBinMathOpMir(.@"and", Type.usize, .{ .register = reg }, .{ .register = tmp_reg });
|
||||
try self.genBinOpMir(.@"and", Type.usize, .{ .register = reg }, .{ .register = tmp_reg });
|
||||
}
|
||||
},
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user