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Merge pull request #12095 from joachimschmidt557/stage2-arm
stage2 ARM: add integer div+mod with constant power-of-twos
This commit is contained in:
Joachim Schmidt
GitHub
commit
1fee9eac8b
@ -567,6 +567,12 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.xor => try self.airBinOp(inst, .xor),
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.shr => try self.airBinOp(inst, .shr),
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.shr_exact => try self.airBinOp(inst, .shr_exact),
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.div_float => try self.airBinOp(inst, .div_float),
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.div_trunc => try self.airBinOp(inst, .div_trunc),
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.div_floor => try self.airBinOp(inst, .div_floor),
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.div_exact => try self.airBinOp(inst, .div_exact),
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.rem => try self.airBinOp(inst, .rem),
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.mod => try self.airBinOp(inst, .mod),
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.ptr_add => try self.airPtrArithmetic(inst, .ptr_add),
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.ptr_sub => try self.airPtrArithmetic(inst, .ptr_sub),
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@ -577,8 +583,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.add_sat => try self.airAddSat(inst),
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.sub_sat => try self.airSubSat(inst),
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.mul_sat => try self.airMulSat(inst),
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.rem => try self.airRem(inst),
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.mod => try self.airMod(inst),
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.shl_sat => try self.airShlSat(inst),
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.slice => try self.airSlice(inst),
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@ -604,8 +608,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.mul_with_overflow => try self.airMulWithOverflow(inst),
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.shl_with_overflow => try self.airShlWithOverflow(inst),
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.div_float, .div_trunc, .div_floor, .div_exact => try self.airDiv(inst),
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.cmp_lt => try self.airCmp(inst, .lt),
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.cmp_lte => try self.airCmp(inst, .lte),
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.cmp_eq => try self.airCmp(inst, .eq),
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@ -1729,24 +1731,6 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ extra.lhs, extra.rhs, .none });
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}
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fn airDiv(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement div for {}", .{self.target.cpu.arch});
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airRem(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement rem for {}", .{self.target.cpu.arch});
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airMod(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement mod for {}", .{self.target.cpu.arch});
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airShlSat(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement shl_sat for {}", .{self.target.cpu.arch});
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@ -2878,6 +2862,127 @@ fn binOp(
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else => unreachable,
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}
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},
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.div_float => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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else => unreachable,
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}
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},
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.div_trunc, .div_floor => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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switch (int_info.signedness) {
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.signed => {
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return self.fail("TODO ARM signed integer division", .{});
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},
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.unsigned => {
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switch (rhs) {
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.immediate => |imm| {
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if (std.math.isPowerOfTwo(imm)) {
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const shift = MCValue{ .immediate = std.math.log2_int(u32, imm) };
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return try self.binOp(.shr, lhs, shift, lhs_ty, rhs_ty, metadata);
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} else {
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return self.fail("TODO ARM integer division by constants", .{});
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}
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},
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else => return self.fail("TODO ARM integer division", .{}),
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}
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},
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}
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} else {
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return self.fail("TODO ARM integer division for integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.div_exact => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => return self.fail("TODO ARM div_exact", .{}),
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else => unreachable,
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}
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},
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.rem => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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switch (int_info.signedness) {
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.signed => {
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return self.fail("TODO ARM signed integer mod", .{});
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},
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.unsigned => {
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switch (rhs) {
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.immediate => |imm| {
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if (std.math.isPowerOfTwo(imm)) {
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const log2 = std.math.log2_int(u32, imm);
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const lhs_is_register = lhs == .register;
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (metadata) |md| inst: {
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break :inst Air.refToIndex(md.lhs).?;
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} else null;
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break :blk try self.prepareNewRegForMoving(track_inst, gp, lhs);
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};
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = if (metadata) |md| blk: {
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if (lhs_is_register and self.reuseOperand(md.inst, md.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(md.inst, gp);
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}
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} else try self.register_manager.allocReg(null, gp);
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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try self.truncRegister(lhs_reg, dest_reg, int_info.signedness, log2);
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return MCValue{ .register = dest_reg };
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} else {
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return self.fail("TODO ARM integer mod by constants", .{});
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}
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},
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else => return self.fail("TODO ARM integer mod", .{}),
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}
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},
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}
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} else {
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return self.fail("TODO ARM integer division for integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.mod => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => return self.fail("TODO ARM mod", .{}),
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else => unreachable,
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}
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},
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.addwrap,
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.subwrap,
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.mulwrap,
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