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Merge pull request #8709 from joachimschmidt557/stage2-arm
stage2 ARM: Generate correct code when spilling registers
This commit is contained in:
Jakub Konka
GitHub
commit
15d6efecfb
230
src/codegen.zig
230
src/codegen.zig
@ -928,7 +928,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// TODO separate architectures with registers from
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// stack-based architectures (spu_2)
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if (callee_preserved_regs.len > 0) {
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if (self.register_manager.tryAllocReg(inst)) |reg| {
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if (self.register_manager.tryAllocReg(inst, &.{})) |reg| {
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return MCValue{ .register = registerAlias(reg, abi_size) };
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}
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}
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@ -940,6 +940,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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pub fn spillInstruction(self: *Self, src: LazySrcLoc, reg: Register, inst: *ir.Inst) !void {
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const stack_mcv = try self.allocRegOrMem(inst, false);
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log.debug("spilling {*} to stack mcv {any}", .{ inst, stack_mcv });
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const reg_mcv = self.getResolvedInstValue(inst);
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assert(reg == toCanonicalReg(reg_mcv.register));
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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@ -951,7 +952,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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/// allocated. A second call to `copyToTmpRegister` may return the same register.
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/// This can have a side effect of spilling instructions to the stack to free up a register.
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fn copyToTmpRegister(self: *Self, src: LazySrcLoc, ty: Type, mcv: MCValue) !Register {
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const reg = try self.register_manager.allocRegWithoutTracking();
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const reg = try self.register_manager.allocRegWithoutTracking(&.{});
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try self.genSetReg(src, ty, reg, mcv);
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return reg;
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}
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@ -960,7 +961,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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/// `reg_owner` is the instruction that gets associated with the register in the register table.
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/// This can have a side effect of spilling instructions to the stack to free up a register.
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fn copyToNewRegister(self: *Self, reg_owner: *ir.Inst, mcv: MCValue) !MCValue {
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const reg = try self.register_manager.allocReg(reg_owner);
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const reg = try self.register_manager.allocReg(reg_owner, &.{});
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try self.genSetReg(reg_owner.src, reg_owner.ty, reg, mcv);
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return MCValue{ .register = reg };
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}
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@ -1380,54 +1381,8 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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}
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}
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fn genArmBinOp(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, op: ir.Inst.Tag) !MCValue {
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const lhs = try self.resolveInst(op_lhs);
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const rhs = try self.resolveInst(op_rhs);
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// Destination must be a register
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var dst_mcv: MCValue = undefined;
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var lhs_mcv: MCValue = undefined;
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var rhs_mcv: MCValue = undefined;
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if (self.reuseOperand(inst, 0, lhs)) {
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// LHS is the destination
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// RHS is the source
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lhs_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs;
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rhs_mcv = rhs;
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dst_mcv = lhs_mcv;
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} else if (self.reuseOperand(inst, 1, rhs)) {
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// RHS is the destination
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// LHS is the source
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lhs_mcv = lhs;
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rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs;
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dst_mcv = rhs_mcv;
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} else {
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// TODO save 1 copy instruction by directly allocating the destination register
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// LHS is the destination
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// RHS is the source
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lhs_mcv = try self.copyToNewRegister(inst, lhs);
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rhs_mcv = rhs;
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dst_mcv = lhs_mcv;
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}
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try self.genArmBinOpCode(inst.src, dst_mcv.register, lhs_mcv, rhs_mcv, op);
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return dst_mcv;
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}
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fn genArmBinOpCode(
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self: *Self,
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src: LazySrcLoc,
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dst_reg: Register,
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lhs_mcv: MCValue,
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rhs_mcv: MCValue,
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op: ir.Inst.Tag,
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) !void {
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assert(lhs_mcv == .register or lhs_mcv == .register);
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const swap_lhs_and_rhs = rhs_mcv == .register and lhs_mcv != .register;
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const op1 = if (swap_lhs_and_rhs) rhs_mcv.register else lhs_mcv.register;
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const op2 = if (swap_lhs_and_rhs) lhs_mcv else rhs_mcv;
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const operand = switch (op2) {
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fn armOperandShouldBeRegister(self: *Self, src: LazySrcLoc, mcv: MCValue) !bool {
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return switch (mcv) {
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.none => unreachable,
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.undef => unreachable,
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.dead, .unreach => unreachable,
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@ -1439,15 +1394,142 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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if (imm > std.math.maxInt(u32)) return self.fail(src, "TODO ARM binary arithmetic immediate larger than u32", .{});
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// Load immediate into register if it doesn't fit
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// as an operand
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break :blk Instruction.Operand.fromU32(@intCast(u32, imm)) orelse
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Instruction.Operand.reg(try self.copyToTmpRegister(src, Type.initTag(.u32), op2), Instruction.Operand.Shift.none);
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// in an operand
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break :blk Instruction.Operand.fromU32(@intCast(u32, imm)) == null;
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},
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.register => true,
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.stack_offset,
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.embedded_in_code,
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.memory,
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=> true,
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};
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}
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fn genArmBinOp(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, op: ir.Inst.Tag) !MCValue {
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const lhs = try self.resolveInst(op_lhs);
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const rhs = try self.resolveInst(op_rhs);
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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const lhs_should_be_register = try self.armOperandShouldBeRegister(op_lhs.src, lhs);
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const rhs_should_be_register = try self.armOperandShouldBeRegister(op_rhs.src, rhs);
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const reuse_lhs = lhs_is_register and self.reuseOperand(inst, 0, lhs);
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const reuse_rhs = !reuse_lhs and rhs_is_register and self.reuseOperand(inst, 1, rhs);
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// Destination must be a register
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var dst_mcv: MCValue = undefined;
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var lhs_mcv = lhs;
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var rhs_mcv = rhs;
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var swap_lhs_and_rhs = false;
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// Allocate registers for operands and/or destination
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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if (reuse_lhs) {
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// Allocate 0 or 1 registers
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if (!rhs_is_register and rhs_should_be_register) {
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rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(op_rhs, &.{lhs.register}) };
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branch.inst_table.putAssumeCapacity(op_rhs, rhs_mcv);
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}
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dst_mcv = lhs;
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} else if (reuse_rhs) {
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// Allocate 0 or 1 registers
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if (!lhs_is_register and lhs_should_be_register) {
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lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(op_lhs, &.{rhs.register}) };
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branch.inst_table.putAssumeCapacity(op_lhs, lhs_mcv);
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}
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dst_mcv = rhs;
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swap_lhs_and_rhs = true;
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} else {
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// Allocate 1 or 2 registers
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if (lhs_should_be_register and rhs_should_be_register) {
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if (lhs_is_register and rhs_is_register) {
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{ lhs.register, rhs.register }) };
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} else if (lhs_is_register) {
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// Move RHS to register
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{lhs.register}) };
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rhs_mcv = dst_mcv;
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} else if (rhs_is_register) {
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// Move LHS to register
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{rhs.register}) };
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lhs_mcv = dst_mcv;
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} else {
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// Move LHS and RHS to register
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const regs = try self.register_manager.allocRegs(2, .{ inst, op_rhs }, &.{});
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lhs_mcv = MCValue{ .register = regs[0] };
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rhs_mcv = MCValue{ .register = regs[1] };
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dst_mcv = lhs_mcv;
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branch.inst_table.putAssumeCapacity(op_rhs, rhs_mcv);
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}
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} else if (lhs_should_be_register) {
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// RHS is immediate
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if (lhs_is_register) {
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{lhs.register}) };
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} else {
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
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lhs_mcv = dst_mcv;
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}
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} else if (rhs_should_be_register) {
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// LHS is immediate
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if (rhs_is_register) {
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{rhs.register}) };
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} else {
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
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rhs_mcv = dst_mcv;
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}
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swap_lhs_and_rhs = true;
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} else unreachable; // binary operation on two immediates
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}
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// Move the operands to the newly allocated registers
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if (lhs_mcv == .register and !lhs_is_register) {
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try self.genSetReg(op_lhs.src, op_lhs.ty, lhs_mcv.register, lhs);
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}
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if (rhs_mcv == .register and !rhs_is_register) {
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try self.genSetReg(op_rhs.src, op_rhs.ty, rhs_mcv.register, rhs);
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}
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try self.genArmBinOpCode(
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inst.src,
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dst_mcv.register,
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lhs_mcv,
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rhs_mcv,
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swap_lhs_and_rhs,
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op,
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);
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return dst_mcv;
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}
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fn genArmBinOpCode(
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self: *Self,
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src: LazySrcLoc,
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dst_reg: Register,
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lhs_mcv: MCValue,
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rhs_mcv: MCValue,
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swap_lhs_and_rhs: bool,
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op: ir.Inst.Tag,
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) !void {
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assert(lhs_mcv == .register or rhs_mcv == .register);
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const op1 = if (swap_lhs_and_rhs) rhs_mcv.register else lhs_mcv.register;
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const op2 = if (swap_lhs_and_rhs) lhs_mcv else rhs_mcv;
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const operand = switch (op2) {
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.none => unreachable,
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.undef => unreachable,
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.dead, .unreach => unreachable,
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.compare_flags_unsigned => unreachable,
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.compare_flags_signed => unreachable,
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.ptr_stack_offset => unreachable,
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.ptr_embedded_in_code => unreachable,
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.immediate => |imm| Instruction.Operand.fromU32(@intCast(u32, imm)).?,
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.register => |reg| Instruction.Operand.reg(reg, Instruction.Operand.Shift.none),
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.stack_offset,
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.embedded_in_code,
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.memory,
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=> Instruction.Operand.reg(try self.copyToTmpRegister(src, Type.initTag(.u32), op2), Instruction.Operand.Shift.none),
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=> unreachable,
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};
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switch (op) {
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@ -2613,10 +2695,42 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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const lhs = try self.resolveInst(inst.lhs);
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const rhs = try self.resolveInst(inst.rhs);
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const src_mcv = rhs;
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const dst_mcv = if (lhs != .register) try self.copyToNewRegister(inst.lhs, lhs) else lhs;
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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// lhs should always be a register
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const rhs_should_be_register = try self.armOperandShouldBeRegister(inst.rhs.src, rhs);
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var lhs_mcv = lhs;
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var rhs_mcv = rhs;
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// Allocate registers
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if (rhs_should_be_register) {
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if (!lhs_is_register and !rhs_is_register) {
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const regs = try self.register_manager.allocRegs(2, .{ inst.rhs, inst.lhs }, &.{});
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lhs_mcv = MCValue{ .register = regs[0] };
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rhs_mcv = MCValue{ .register = regs[1] };
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} else if (!rhs_is_register) {
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rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(inst.rhs, &.{}) };
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}
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}
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if (!lhs_is_register) {
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lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(inst.lhs, &.{}) };
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}
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// Move the operands to the newly allocated registers
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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if (lhs_mcv == .register and !lhs_is_register) {
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try self.genSetReg(inst.lhs.src, inst.lhs.ty, lhs_mcv.register, lhs);
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branch.inst_table.putAssumeCapacity(inst.lhs, lhs);
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}
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if (rhs_mcv == .register and !rhs_is_register) {
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try self.genSetReg(inst.rhs.src, inst.rhs.ty, rhs_mcv.register, rhs);
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branch.inst_table.putAssumeCapacity(inst.rhs, rhs);
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}
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// The destination register is not present in the cmp instruction
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try self.genArmBinOpCode(inst.base.src, undefined, lhs_mcv, rhs_mcv, false, .cmp_eq);
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try self.genArmBinOpCode(inst.base.src, dst_mcv.register, dst_mcv, src_mcv, .cmp_eq);
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const info = inst.lhs.ty.intInfo(self.target.*);
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return switch (info.signedness) {
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.signed => MCValue{ .compare_flags_signed = op },
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@ -1,5 +1,6 @@
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const std = @import("std");
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const math = std.math;
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const mem = std.mem;
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const assert = std.debug.assert;
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const Allocator = std.mem.Allocator;
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const ir = @import("ir.zig");
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@ -66,8 +67,13 @@ pub fn RegisterManager(
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}
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/// Returns `null` if all registers are allocated.
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pub fn tryAllocRegs(self: *Self, comptime count: comptime_int, insts: [count]*ir.Inst) ?[count]Register {
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if (self.tryAllocRegsWithoutTracking(count)) |regs| {
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pub fn tryAllocRegs(
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self: *Self,
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comptime count: comptime_int,
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insts: [count]*ir.Inst,
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exceptions: []Register,
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) ?[count]Register {
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if (self.tryAllocRegsWithoutTracking(count, exceptions)) |regs| {
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for (regs) |reg, i| {
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const index = reg.allocIndex().?; // allocIndex() on a callee-preserved reg should never return null
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self.registers[index] = insts[i];
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@ -81,21 +87,30 @@ pub fn RegisterManager(
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}
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/// Returns `null` if all registers are allocated.
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pub fn tryAllocReg(self: *Self, inst: *ir.Inst) ?Register {
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return if (tryAllocRegs(self, 1, .{inst})) |regs| regs[0] else null;
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pub fn tryAllocReg(self: *Self, inst: *ir.Inst, exceptions: []Register) ?Register {
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return if (tryAllocRegs(self, 1, .{inst}, exceptions)) |regs| regs[0] else null;
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}
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pub fn allocRegs(self: *Self, comptime count: comptime_int, insts: [count]*ir.Inst) ![count]Register {
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pub fn allocRegs(
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self: *Self,
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comptime count: comptime_int,
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insts: [count]*ir.Inst,
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exceptions: []Register,
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) ![count]Register {
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comptime assert(count > 0 and count <= callee_preserved_regs.len);
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assert(count + exceptions.len <= callee_preserved_regs.len);
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return self.tryAllocRegs(count, insts) orelse blk: {
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return self.tryAllocRegs(count, insts, exceptions) orelse blk: {
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// We'll take over the first count registers. Spill
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// the instructions that were previously there to a
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// stack allocations.
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var regs: [count]Register = undefined;
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std.mem.copy(Register, ®s, callee_preserved_regs[0..count]);
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var i: usize = 0;
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for (callee_preserved_regs) |reg| {
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if (i >= count) break;
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if (mem.indexOfScalar(Register, exceptions, reg) != null) continue;
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regs[i] = reg;
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for (regs) |reg, i| {
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const index = reg.allocIndex().?; // allocIndex() on a callee-preserved reg should never return null
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if (self.isRegFree(reg)) {
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self.markRegUsed(reg);
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@ -104,21 +119,28 @@ pub fn RegisterManager(
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try self.getFunction().spillInstruction(spilled_inst.src, reg, spilled_inst);
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}
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self.registers[index] = insts[i];
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i += 1;
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}
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break :blk regs;
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};
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}
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pub fn allocReg(self: *Self, inst: *ir.Inst) !Register {
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return (try self.allocRegs(1, .{inst}))[0];
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pub fn allocReg(self: *Self, inst: *ir.Inst, exceptions: []Register) !Register {
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return (try self.allocRegs(1, .{inst}, exceptions))[0];
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}
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/// Does not track the registers.
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/// Returns `null` if not enough registers are free.
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pub fn tryAllocRegsWithoutTracking(self: *Self, comptime count: comptime_int) ?[count]Register {
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pub fn tryAllocRegsWithoutTracking(
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self: *Self,
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comptime count: comptime_int,
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exceptions: []Register,
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) ?[count]Register {
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comptime if (callee_preserved_regs.len == 0) return null;
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comptime assert(count > 0 and count <= callee_preserved_regs.len);
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assert(count + exceptions.len <= callee_preserved_regs.len);
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const free_registers = @popCount(FreeRegInt, self.free_registers);
|
||||
if (free_registers < count) return null;
|
||||
@ -127,30 +149,35 @@ pub fn RegisterManager(
|
||||
var i: usize = 0;
|
||||
for (callee_preserved_regs) |reg| {
|
||||
if (i >= count) break;
|
||||
if (mem.indexOfScalar(Register, exceptions, reg) != null) continue;
|
||||
if (self.isRegFree(reg)) {
|
||||
regs[i] = reg;
|
||||
i += 1;
|
||||
}
|
||||
}
|
||||
return regs;
|
||||
|
||||
return if (i < count) null else regs;
|
||||
}
|
||||
|
||||
/// Does not track the register.
|
||||
/// Returns `null` if all registers are allocated.
|
||||
pub fn tryAllocRegWithoutTracking(self: *Self) ?Register {
|
||||
return if (self.tryAllocRegsWithoutTracking(1)) |regs| regs[0] else null;
|
||||
pub fn tryAllocRegWithoutTracking(self: *Self, exceptions: []Register) ?Register {
|
||||
return if (self.tryAllocRegsWithoutTracking(1, exceptions)) |regs| regs[0] else null;
|
||||
}
|
||||
|
||||
/// Does not track the registers
|
||||
pub fn allocRegsWithoutTracking(self: *Self, comptime count: comptime_int) ![count]Register {
|
||||
return self.tryAllocRegsWithoutTracking(count) orelse blk: {
|
||||
pub fn allocRegsWithoutTracking(self: *Self, comptime count: comptime_int, exceptions: []Register) ![count]Register {
|
||||
return self.tryAllocRegsWithoutTracking(count, exceptions) orelse blk: {
|
||||
// We'll take over the first count registers. Spill
|
||||
// the instructions that were previously there to a
|
||||
// stack allocations.
|
||||
var regs: [count]Register = undefined;
|
||||
std.mem.copy(Register, ®s, callee_preserved_regs[0..count]);
|
||||
var i: usize = 0;
|
||||
for (callee_preserved_regs) |reg| {
|
||||
if (i >= count) break;
|
||||
if (mem.indexOfScalar(Register, exceptions, reg) != null) continue;
|
||||
regs[i] = reg;
|
||||
|
||||
for (regs) |reg, i| {
|
||||
const index = reg.allocIndex().?; // allocIndex() on a callee-preserved reg should never return null
|
||||
if (!self.isRegFree(reg)) {
|
||||
const spilled_inst = self.registers[index].?;
|
||||
@ -158,6 +185,8 @@ pub fn RegisterManager(
|
||||
self.registers[index] = null;
|
||||
self.markRegFree(reg);
|
||||
}
|
||||
|
||||
i += 1;
|
||||
}
|
||||
|
||||
break :blk regs;
|
||||
@ -165,8 +194,8 @@ pub fn RegisterManager(
|
||||
}
|
||||
|
||||
/// Does not track the register.
|
||||
pub fn allocRegWithoutTracking(self: *Self) !Register {
|
||||
return (try self.allocRegsWithoutTracking(1))[0];
|
||||
pub fn allocRegWithoutTracking(self: *Self, exceptions: []Register) !Register {
|
||||
return (try self.allocRegsWithoutTracking(1, exceptions))[0];
|
||||
}
|
||||
|
||||
/// Allocates the specified register with the specified
|
||||
@ -270,9 +299,9 @@ test "tryAllocReg: no spilling" {
|
||||
try std.testing.expect(!function.register_manager.isRegAllocated(.r2));
|
||||
try std.testing.expect(!function.register_manager.isRegAllocated(.r3));
|
||||
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r2), function.register_manager.tryAllocReg(&mock_instruction));
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r3), function.register_manager.tryAllocReg(&mock_instruction));
|
||||
try std.testing.expectEqual(@as(?MockRegister, null), function.register_manager.tryAllocReg(&mock_instruction));
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r2), function.register_manager.tryAllocReg(&mock_instruction, &.{}));
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r3), function.register_manager.tryAllocReg(&mock_instruction, &.{}));
|
||||
try std.testing.expectEqual(@as(?MockRegister, null), function.register_manager.tryAllocReg(&mock_instruction, &.{}));
|
||||
|
||||
try std.testing.expect(function.register_manager.isRegAllocated(.r2));
|
||||
try std.testing.expect(function.register_manager.isRegAllocated(.r3));
|
||||
@ -301,16 +330,16 @@ test "allocReg: spilling" {
|
||||
try std.testing.expect(!function.register_manager.isRegAllocated(.r2));
|
||||
try std.testing.expect(!function.register_manager.isRegAllocated(.r3));
|
||||
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r2), try function.register_manager.allocReg(&mock_instruction));
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r3), try function.register_manager.allocReg(&mock_instruction));
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r2), try function.register_manager.allocReg(&mock_instruction, &.{}));
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r3), try function.register_manager.allocReg(&mock_instruction, &.{}));
|
||||
|
||||
// Spill a register
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r2), try function.register_manager.allocReg(&mock_instruction));
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r2), try function.register_manager.allocReg(&mock_instruction, &.{}));
|
||||
try std.testing.expectEqualSlices(MockRegister, &[_]MockRegister{.r2}, function.spilled.items);
|
||||
|
||||
// No spilling necessary
|
||||
function.register_manager.freeReg(.r3);
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r3), try function.register_manager.allocReg(&mock_instruction));
|
||||
try std.testing.expectEqual(@as(?MockRegister, .r3), try function.register_manager.allocReg(&mock_instruction, &.{}));
|
||||
try std.testing.expectEqualSlices(MockRegister, &[_]MockRegister{.r2}, function.spilled.items);
|
||||
}
|
||||
|
||||
|
||||
@ -458,4 +458,57 @@ pub fn addCases(ctx: *TestContext) !void {
|
||||
"",
|
||||
);
|
||||
}
|
||||
|
||||
{
|
||||
var case = ctx.exe("spilling registers", linux_arm);
|
||||
case.addCompareOutput(
|
||||
\\export fn _start() noreturn {
|
||||
\\ assert(add(3, 4) == 791);
|
||||
\\ exit();
|
||||
\\}
|
||||
\\
|
||||
\\fn add(a: u32, b: u32) u32 {
|
||||
\\ const x: u32 = blk: {
|
||||
\\ const c = a + b; // 7
|
||||
\\ const d = a + c; // 10
|
||||
\\ const e = d + b; // 14
|
||||
\\ const f = d + e; // 24
|
||||
\\ const g = e + f; // 38
|
||||
\\ const h = f + g; // 62
|
||||
\\ const i = g + h; // 100
|
||||
\\ const j = i + d; // 110
|
||||
\\ const k = i + j; // 210
|
||||
\\ const l = k + c; // 217
|
||||
\\ const m = l + d; // 227
|
||||
\\ const n = m + e; // 241
|
||||
\\ const o = n + f; // 265
|
||||
\\ const p = o + g; // 303
|
||||
\\ const q = p + h; // 365
|
||||
\\ const r = q + i; // 465
|
||||
\\ const s = r + j; // 575
|
||||
\\ const t = s + k; // 785
|
||||
\\ break :blk t;
|
||||
\\ };
|
||||
\\ const y = x + a; // 788
|
||||
\\ const z = y + a; // 791
|
||||
\\ return z;
|
||||
\\}
|
||||
\\
|
||||
\\fn assert(ok: bool) void {
|
||||
\\ if (!ok) unreachable;
|
||||
\\}
|
||||
\\
|
||||
\\fn exit() noreturn {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (1),
|
||||
\\ [arg1] "{r0}" (0)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
"",
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user