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std.debug.cpu_context: add Sparc context
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@ -10,6 +10,7 @@ else switch (native_arch) {
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.loongarch32, .loongarch64 => LoongArch,
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.mips, .mipsel, .mips64, .mips64el => Mips,
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.powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,
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.sparc, .sparc64 => Sparc,
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.riscv32, .riscv32be, .riscv64, .riscv64be => Riscv,
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.s390x => S390x,
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.x86 => X86,
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@ -858,6 +859,93 @@ const Powerpc = extern struct {
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}
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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const Sparc = extern struct {
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g: [8]Gpr,
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o: [8]Gpr,
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l: [8]Gpr,
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i: [8]Gpr,
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pc: Gpr,
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pub const Gpr = if (native_arch == .sparc64) u64 else u32;
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pub inline fn current() Sparc {
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var ctx: Sparc = undefined;
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asm volatile (if (Gpr == u64)
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\\ stx %g0, [%l0 + 0]
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\\ stx %g1, [%l0 + 8]
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\\ stx %g2, [%l0 + 16]
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\\ stx %g3, [%l0 + 24]
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\\ stx %g4, [%l0 + 32]
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\\ stx %g5, [%l0 + 40]
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\\ stx %g6, [%l0 + 48]
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\\ stx %g7, [%l0 + 56]
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\\ stx %o0, [%l0 + 64]
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\\ stx %o1, [%l0 + 72]
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\\ stx %o2, [%l0 + 80]
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\\ stx %o3, [%l0 + 88]
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\\ stx %o4, [%l0 + 96]
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\\ stx %o5, [%l0 + 104]
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\\ stx %o6, [%l0 + 112]
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\\ stx %o7, [%l0 + 120]
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\\ stx %l0, [%l0 + 128]
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\\ stx %l1, [%l0 + 136]
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\\ stx %l2, [%l0 + 144]
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\\ stx %l3, [%l0 + 152]
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\\ stx %l4, [%l0 + 160]
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\\ stx %l5, [%l0 + 168]
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\\ stx %l6, [%l0 + 176]
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\\ stx %l7, [%l0 + 184]
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\\ stx %i0, [%l0 + 192]
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\\ stx %i1, [%l0 + 200]
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\\ stx %i2, [%l0 + 208]
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\\ stx %i3, [%l0 + 216]
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\\ stx %i4, [%l0 + 224]
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\\ stx %i5, [%l0 + 232]
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\\ stx %i6, [%l0 + 240]
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\\ stx %i7, [%l0 + 248]
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\\ call 1f
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\\ stx %o7, [%l0 + 256]
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\\1:
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else
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\\ std %g0, [%l0 + 0]
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\\ std %g2, [%l0 + 8]
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\\ std %g4, [%l0 + 16]
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\\ std %g6, [%l0 + 24]
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\\ std %o0, [%l0 + 32]
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\\ std %o2, [%l0 + 40]
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\\ std %o4, [%l0 + 48]
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\\ std %o6, [%l0 + 56]
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\\ std %l0, [%l0 + 64]
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\\ std %l2, [%l0 + 72]
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\\ std %l4, [%l0 + 80]
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\\ std %l6, [%l0 + 88]
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\\ std %i0, [%l0 + 96]
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\\ std %i2, [%l0 + 104]
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\\ std %i4, [%l0 + 112]
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\\ std %i6, [%l0 + 120]
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\\ call 1f
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\\ st %o7, [%l0 + 128]
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\\1:
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:
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: [gprs] "{l0}" (&ctx),
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: .{ .o7 = true, .memory = true });
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return ctx;
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}
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pub fn dwarfRegisterBytes(ctx: *Sparc, register_num: u16) DwarfRegisterError![]u8 {
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switch (register_num) {
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0...7 => return @ptrCast(&ctx.g[register_num]),
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8...15 => return @ptrCast(&ctx.o[register_num - 8]),
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16...23 => return @ptrCast(&ctx.l[register_num - 16]),
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24...31 => return @ptrCast(&ctx.i[register_num - 24]),
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32 => return @ptrCast(&ctx.pc),
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else => return error.InvalidRegister,
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}
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}
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};
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/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
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const Riscv = extern struct {
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/// The numbered general-purpose registers r0 - r31. r0 must be zero.
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