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x64: handle signed mul_with_overflow for non-pow-2 ints
This commit is contained in:
Jakub Konka
parent
ebfc2825ab
commit
0fc1e8b54f
@ -1086,29 +1086,7 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {
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// have to be removed. this only happens if the dst if not a power-of-two size.
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const dst_bit_size = dst_ty.bitSize(self.target.*);
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if (!math.isPowerOfTwo(dst_bit_size) or dst_bit_size < 8) {
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const max_reg_bit_width = Register.rax.size();
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const shift = @intCast(u6, max_reg_bit_width - dst_ty.bitSize(self.target.*));
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const mask = (~@as(u64, 0)) >> shift;
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try self.genBinMathOpMir(.@"and", Type.usize, .{ .register = reg }, .{ .immediate = mask });
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if (src_ty.intInfo(self.target.*).signedness == .signed) {
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_ = try self.addInst(.{
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.tag = .sal,
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.ops = (Mir.Ops{
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.reg1 = reg,
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = shift },
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});
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_ = try self.addInst(.{
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.tag = .sar,
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.ops = (Mir.Ops{
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.reg1 = reg,
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = shift },
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});
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}
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try self.truncateRegister(dst_ty, reg);
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}
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return self.finishAir(inst, .{ .register = reg }, .{ ty_op.operand, .none, .none });
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@ -1478,31 +1456,119 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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switch (ty.zigTypeTag()) {
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.Vector => return self.fail("TODO implement mul_with_overflow for Vector type", .{}),
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.Int => {
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = null;
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const int_info = ty.intInfo(self.target.*);
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if (int_info.bits > 64) {
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return self.fail("TODO implement mul_with_overflow for Ints larger than 64bits", .{});
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}
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// Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
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try self.register_manager.getReg(.rax, inst);
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try self.register_manager.getReg(.rdx, null);
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self.register_manager.freezeRegs(&.{ .rax, .rdx });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rdx });
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if (math.isPowerOfTwo(int_info.bits)) {
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// Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
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try self.register_manager.getReg(.rax, inst);
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try self.register_manager.getReg(.rdx, null);
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self.register_manager.freezeRegs(&.{ .rax, .rdx });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rdx });
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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try self.genIntMulDivOpMir(switch (int_info.signedness) {
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.signed => .imul,
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.unsigned => .mul,
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}, ty, int_info.signedness, lhs, rhs);
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const result: MCValue = switch (int_info.signedness) {
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.signed => .{ .register_overflow_signed = .rax },
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.unsigned => .{ .register_overflow_unsigned = .rax },
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};
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break :result result;
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}
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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try self.genIntMulDivOpMir(switch (int_info.signedness) {
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.signed => .imul,
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.unsigned => .mul,
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}, ty, int_info.signedness, lhs, rhs);
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rhs.freezeIfRegister(&self.register_manager);
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defer rhs.unfreezeIfRegister(&self.register_manager);
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const result: MCValue = switch (int_info.signedness) {
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.signed => .{ .register_overflow_signed = .rax },
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.unsigned => .{ .register_overflow_unsigned = .rax },
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// TODO check if we could reuse rhs instead, and swap the values out.
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const dst_mcv = blk: {
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if (self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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if (lhs.isRegister()) break :blk lhs;
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}
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break :blk MCValue{ .register = try self.copyToTmpRegister(ty, lhs) };
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};
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break :result result;
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dst_mcv.freezeIfRegister(&self.register_manager);
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defer dst_mcv.unfreezeIfRegister(&self.register_manager);
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const rhs_mcv = blk: {
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if (rhs.isRegister() or rhs.isMemory()) break :blk rhs;
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break :blk MCValue{ .register = try self.copyToTmpRegister(ty, rhs) };
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};
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rhs_mcv.freezeIfRegister(&self.register_manager);
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defer rhs_mcv.unfreezeIfRegister(&self.register_manager);
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const tuple_ty = self.air.typeOfIndex(inst);
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const tuple_size = @intCast(u32, tuple_ty.abiSize(self.target.*));
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const tuple_align = tuple_ty.abiAlignment(self.target.*);
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const overflow_bit_offset = @intCast(i32, tuple_ty.structFieldOffset(1, self.target.*));
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const stack_offset = @intCast(i32, try self.allocMem(inst, tuple_size, tuple_align));
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const extended_ty = switch (int_info.signedness) {
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.signed => Type.isize,
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.unsigned => ty,
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};
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try self.genIntMulComplexOpMir(extended_ty, dst_mcv, rhs_mcv);
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const temp_regs = try self.register_manager.allocRegs(3, .{ null, null, null });
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self.register_manager.freezeRegs(&temp_regs);
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defer self.register_manager.unfreezeRegs(&temp_regs);
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const overflow_reg = temp_regs[0];
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const flags: u2 = switch (int_info.signedness) {
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.signed => 0b00,
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.unsigned => 0b10,
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};
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_ = try self.addInst(.{
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.tag = .cond_set_byte_overflow,
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.ops = (Mir.Ops{
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.reg1 = overflow_reg.to8(),
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.flags = flags,
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}).encode(),
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.data = undefined,
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});
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const scratch_reg = temp_regs[1];
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try self.genSetReg(extended_ty, scratch_reg, dst_mcv);
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try self.truncateRegister(ty, scratch_reg);
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try self.genBinMathOpMir(.cmp, extended_ty, dst_mcv, .{ .register = scratch_reg });
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const eq_reg = temp_regs[2];
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_ = try self.addInst(.{
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.tag = .cond_set_byte_eq_ne,
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.ops = (Mir.Ops{
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.reg1 = eq_reg.to8(),
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.flags = 0b00,
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}).encode(),
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.data = undefined,
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});
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try self.genBinMathOpMir(
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.@"or",
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Type.u8,
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.{ .register = overflow_reg },
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.{ .register = eq_reg },
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);
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try self.genSetStack(ty, stack_offset, .{ .register = scratch_reg }, .{});
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try self.genSetStack(Type.initTag(.u1), stack_offset - overflow_bit_offset, .{
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.register = overflow_reg.to8(),
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}, .{});
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break :result MCValue{ .stack_offset = stack_offset };
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},
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else => unreachable,
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}
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@ -1648,7 +1714,7 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa
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}).encode(),
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.data = undefined,
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});
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try self.genBinMathOpMir(.add, Type.isize, .{ .register = divisor.to64() }, .{ .register = .rax });
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try self.genBinMathOpMir(.add, Type.isize, .{ .register = divisor }, .{ .register = .rax });
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return MCValue{ .register = divisor };
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}
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@ -2222,8 +2288,8 @@ fn genSliceElemPtr(self: *Self, lhs: Air.Inst.Ref, rhs: Air.Inst.Ref) !MCValue {
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}
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// TODO we could allocate register here, but need to expect addr register and potentially
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// offset register.
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try self.genBinMathOpMir(.add, slice_ptr_field_type, .{ .register = addr_reg.to64() }, .{
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.register = offset_reg.to64(),
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try self.genBinMathOpMir(.add, slice_ptr_field_type, .{ .register = addr_reg }, .{
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.register = offset_reg,
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});
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return MCValue{ .register = addr_reg.to64() };
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}
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@ -2315,7 +2381,7 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
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// TODO we could allocate register here, but need to expect addr register and potentially
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// offset register.
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const dst_mcv = try self.allocRegOrMem(inst, false);
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try self.genBinMathOpMir(.add, array_ty, .{ .register = addr_reg.to64() }, .{ .register = offset_reg.to64() });
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try self.genBinMathOpMir(.add, Type.usize, .{ .register = addr_reg }, .{ .register = offset_reg });
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try self.load(dst_mcv, .{ .register = addr_reg.to64() }, array_ty);
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break :result dst_mcv;
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};
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@ -3178,8 +3244,8 @@ fn genBinMathOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MC
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_ = try self.addInst(.{
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.tag = mir_tag,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(dst_reg, @divExact(src_reg.size(), 8)),
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.reg2 = src_reg,
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.reg1 = registerAlias(dst_reg, abi_size),
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.reg2 = registerAlias(src_reg, abi_size),
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}).encode(),
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.data = undefined,
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});
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@ -6531,3 +6597,36 @@ fn shiftRegister(self: *Self, reg: Register, shift: u8) !void {
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});
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}
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}
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/// Truncates the value in the register in place.
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/// Clobbers any remaining bits.
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fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
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const int_info = ty.intInfo(self.target.*);
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const max_reg_bit_width = Register.rax.size();
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switch (int_info.signedness) {
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.signed => {
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const shift = @intCast(u6, max_reg_bit_width - int_info.bits);
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_ = try self.addInst(.{
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.tag = .sal,
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.ops = (Mir.Ops{
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.reg1 = reg.to64(),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = shift },
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});
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_ = try self.addInst(.{
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.tag = .sar,
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.ops = (Mir.Ops{
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.reg1 = reg.to64(),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = shift },
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});
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},
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.unsigned => {
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const shift = @intCast(u6, max_reg_bit_width - int_info.bits);
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const mask = (~@as(u64, 0)) >> shift;
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try self.genBinMathOpMir(.@"and", Type.usize, .{ .register = reg }, .{ .immediate = mask });
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},
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}
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}
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@ -1383,7 +1383,7 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {
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.sub => OpCode.oneByte(if (is_one_byte) 0x2a else 0x2b),
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.xor => OpCode.oneByte(if (is_one_byte) 0x32 else 0x33),
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.@"and" => OpCode.oneByte(if (is_one_byte) 0x22 else 0x23),
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.@"or" => OpCode.oneByte(if (is_one_byte) 0x0b else 0x0b),
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.@"or" => OpCode.oneByte(if (is_one_byte) 0x0a else 0x0b),
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.sbb => OpCode.oneByte(if (is_one_byte) 0x1a else 0x1b),
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.cmp => OpCode.oneByte(if (is_one_byte) 0x3a else 0x3b),
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.mov => OpCode.oneByte(if (is_one_byte) 0x8a else 0x8b),
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