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x86_64: implement element access
This commit is contained in:
Jacob Young
parent
870443f7fa
commit
0d9079f466
@ -2492,8 +2492,6 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
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.atomic_store_seq_cst => try cg.airAtomicStore(inst, .seq_cst),
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.array_elem_val => try cg.airArrayElemVal(inst),
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.slice_elem_val => try cg.airSliceElemVal(inst),
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.ptr_elem_val => try cg.airPtrElemVal(inst),
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.optional_payload => try cg.airOptionalPayload(inst),
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.unwrap_errunion_err => try cg.airUnwrapErrUnionErr(inst),
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@ -3995,7 +3993,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
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var slot = try cg.tempFromValue(cg.typeOfIndex(inst), .{ .load_frame = .{
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.index = .ret_addr,
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} });
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while (try slot.toAnyReg(cg)) {}
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while (try slot.toRegClass(true, .general_purpose, cg)) {}
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try slot.moveTo(inst, cg);
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},
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.frame_addr => if (use_old) try cg.airFrameAddress(inst) else {
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@ -9445,7 +9443,111 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
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try ops[0].toOffset(0, cg);
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try ops[0].moveTo(inst, cg);
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},
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.slice_elem_ptr, .ptr_elem_ptr => |tag| if (use_old) switch (tag) {
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.slice_elem_val, .ptr_elem_val => |air_tag| if (use_old) switch (air_tag) {
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else => unreachable,
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.slice_elem_val => try cg.airSliceElemVal(inst),
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.ptr_elem_val => try cg.airPtrElemVal(inst),
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} else {
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const bin_op = air_datas[@intFromEnum(inst)].bin_op;
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var ops = try cg.tempsFromOperands(inst, .{ bin_op.lhs, bin_op.rhs });
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switch (air_tag) {
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else => unreachable,
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.slice_elem_val => try ops[0].toLimb(0, cg),
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.ptr_elem_val => {},
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}
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var res: [1]Temp = undefined;
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const res_ty = cg.typeOfIndex(inst);
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cg.select(&res, &.{res_ty}, &ops, comptime &.{ .{
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.dst_constraints = .{.{ .int = .byte }},
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.patterns = &.{
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.{ .src = .{ .to_gpr, .simm32 } },
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.{ .src = .{ .to_gpr, .to_gpr } },
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},
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.dst_temps = .{.{ .rc = .general_purpose }},
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.each = .{ .once = &.{
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.{ ._, ._, .movzx, .dst0d, .leai(.byte, .src0, .src1), ._, ._ },
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} },
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}, .{
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.dst_constraints = .{.{ .int = .word }},
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.patterns = &.{
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.{ .src = .{ .to_gpr, .simm32 } },
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.{ .src = .{ .to_gpr, .to_gpr } },
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},
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.dst_temps = .{.{ .rc = .general_purpose }},
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.each = .{ .once = &.{
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.{ ._, ._, .movzx, .dst0d, .leasi(.word, .src0, .@"2", .src1), ._, ._ },
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} },
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}, .{
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.dst_constraints = .{.{ .int = .dword }},
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.patterns = &.{
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.{ .src = .{ .to_gpr, .simm32 } },
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.{ .src = .{ .to_gpr, .to_gpr } },
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},
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.dst_temps = .{.{ .rc = .general_purpose }},
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.each = .{ .once = &.{
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.{ ._, ._, .mov, .dst0d, .leasi(.dword, .src0, .@"4", .src1), ._, ._ },
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} },
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}, .{
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.required_features = .{ .@"64bit", null, null, null },
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.dst_constraints = .{.{ .int = .qword }},
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.patterns = &.{
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.{ .src = .{ .to_gpr, .simm32 } },
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.{ .src = .{ .to_gpr, .to_gpr } },
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},
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.dst_temps = .{.{ .rc = .general_purpose }},
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.each = .{ .once = &.{
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.{ ._, ._, .mov, .dst0q, .leasi(.qword, .src0, .@"8", .src1), ._, ._ },
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} },
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} }) catch |err| switch (err) {
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error.SelectFailed => switch (res_ty.abiSize(zcu)) {
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0 => res[0] = try cg.tempFromValue(res_ty, .none),
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else => |elem_size| {
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while (true) for (&ops) |*op| {
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if (try op.toRegClass(true, .general_purpose, cg)) break;
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} else break;
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const lhs_reg = ops[0].unwrap(cg).temp.tracking(cg).short.register.to64();
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const rhs_reg = ops[1].unwrap(cg).temp.tracking(cg).short.register.to64();
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if (!std.math.isPowerOfTwo(elem_size)) {
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try cg.spillEflagsIfOccupied();
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try cg.asmRegisterRegisterImmediate(
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.{ .i_, .mul },
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rhs_reg,
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rhs_reg,
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.u(elem_size),
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);
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try cg.asmRegisterMemory(.{ ._, .lea }, lhs_reg, .{
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.base = .{ .reg = lhs_reg },
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.mod = .{ .rm = .{ .size = .qword, .index = rhs_reg } },
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});
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} else if (elem_size > 8) {
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try cg.spillEflagsIfOccupied();
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try cg.asmRegisterImmediate(
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.{ ._l, .sh },
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rhs_reg,
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.u(std.math.log2_int(u64, elem_size)),
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);
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try cg.asmRegisterMemory(.{ ._, .lea }, lhs_reg, .{
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.base = .{ .reg = lhs_reg },
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.mod = .{ .rm = .{ .size = .qword, .index = rhs_reg } },
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});
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} else try cg.asmRegisterMemory(.{ ._, .lea }, lhs_reg, .{
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.base = .{ .reg = lhs_reg },
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.mod = .{ .rm = .{
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.size = .qword,
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.index = rhs_reg,
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.scale = .fromFactor(@intCast(elem_size)),
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} },
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});
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res[0] = try ops[0].load(res_ty, cg);
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},
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},
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else => |e| return e,
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};
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if (ops[0].index != res[0].index) try ops[0].die(cg);
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if (ops[1].index != res[0].index) try ops[1].die(cg);
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try res[0].moveTo(inst, cg);
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},
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.slice_elem_ptr, .ptr_elem_ptr => |air_tag| if (use_old) switch (air_tag) {
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else => unreachable,
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.slice_elem_ptr => try cg.airSliceElemPtr(inst),
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.ptr_elem_ptr => try cg.airPtrElemPtr(inst),
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@ -9453,7 +9555,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
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const ty_pl = air_datas[@intFromEnum(inst)].ty_pl;
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const bin_op = cg.air.extraData(Air.Bin, ty_pl.payload).data;
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var ops = try cg.tempsFromOperands(inst, .{ bin_op.lhs, bin_op.rhs });
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switch (tag) {
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switch (air_tag) {
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else => unreachable,
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.slice_elem_ptr => try ops[0].toLimb(0, cg),
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.ptr_elem_ptr => {},
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@ -9463,7 +9565,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void {
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const elem_size = dst_ty.childType(zcu).abiSize(zcu);
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if (elem_size == 0) break :zero_offset;
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while (true) for (&ops) |*op| {
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if (try op.toAnyReg(cg)) break;
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if (try op.toRegClass(true, .general_purpose, cg)) break;
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} else break;
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const lhs_reg = ops[0].unwrap(cg).temp.tracking(cg).short.register.to64();
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const rhs_reg = ops[1].unwrap(cg).temp.tracking(cg).short.register.to64();
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@ -27718,6 +27820,7 @@ const Temp = struct {
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},
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};
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const new_temp_index = cg.next_temp_index;
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try cg.register_manager.getReg(new_reg, new_temp_index.toIndex());
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cg.temp_type[@intFromEnum(new_temp_index)] = ty;
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try cg.genSetReg(new_reg, ty, val, .{});
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new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });
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@ -27727,27 +27830,6 @@ const Temp = struct {
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return true;
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}
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fn toAnyReg(temp: *Temp, cg: *CodeGen) !bool {
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const val, const ty = switch (temp.unwrap(cg)) {
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.ref => |ref| .{ temp.tracking(cg).short, cg.typeOf(ref) },
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.temp => |temp_index| val: {
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const temp_tracking = temp_index.tracking(cg);
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if (temp_tracking.short == .register) return false;
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break :val .{ temp_tracking.short, temp_index.typeOf(cg) };
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},
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};
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const new_temp_index = cg.next_temp_index;
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cg.temp_type[@intFromEnum(new_temp_index)] = ty;
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const new_reg =
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try cg.register_manager.allocReg(new_temp_index.toIndex(), cg.regSetForType(ty));
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try cg.genSetReg(new_reg, ty, val, .{});
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new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });
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try temp.die(cg);
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cg.next_temp_index = @enumFromInt(@intFromEnum(new_temp_index) + 1);
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temp.* = .{ .index = new_temp_index.toIndex() };
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return true;
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}
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fn toRegClass(temp: *Temp, mut: bool, rc: Register.Class, cg: *CodeGen) !bool {
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const val = temp.tracking(cg).short;
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if (!mut or temp.isMut(cg)) switch (val) {
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@ -27769,7 +27851,7 @@ const Temp = struct {
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fn toPair(first_temp: *Temp, second_temp: *Temp, cg: *CodeGen) !void {
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while (true) for ([_]*Temp{ first_temp, second_temp }) |part_temp| {
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if (try part_temp.toAnyReg(cg)) break;
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if (try part_temp.toRegClass(true, .general_purpose, cg)) break;
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} else break;
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const first_temp_tracking = first_temp.unwrap(cg).temp.tracking(cg);
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const second_temp_tracking = second_temp.unwrap(cg).temp.tracking(cg);
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@ -27824,12 +27906,12 @@ const Temp = struct {
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.load_got,
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.load_tlv,
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.load_frame,
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=> return temp.toAnyReg(cg),
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=> return temp.toRegClass(true, .general_purpose, cg),
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.lea_symbol => |sym_off| {
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const off = sym_off.off;
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if (off == 0) return false;
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try temp.toOffset(-off, cg);
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while (try temp.toAnyReg(cg)) {}
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while (try temp.toRegClass(true, .general_purpose, cg)) {}
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try temp.toOffset(off, cg);
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return true;
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},
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@ -27868,24 +27950,16 @@ const Temp = struct {
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}
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fn load(ptr: *Temp, val_ty: Type, cg: *CodeGen) !Temp {
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const val_abi_size: u32 = @intCast(val_ty.abiSize(cg.pt.zcu));
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const val = try cg.tempAlloc(val_ty);
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switch (val.tracking(cg).short) {
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else => |mcv| std.debug.panic("{s}: {}\n", .{ @src().fn_name, mcv }),
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.register => |val_reg| {
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while (try ptr.toLea(cg)) {}
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switch (val_reg.class()) {
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.general_purpose => try cg.asmRegisterMemory(
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.{ ._, .mov },
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registerAlias(val_reg, val_abi_size),
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try ptr.tracking(cg).short.deref().mem(cg, .{ .size = cg.memSize(val_ty) }),
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),
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else => |mcv| std.debug.panic("{s}: {}\n", .{ @src().fn_name, mcv }),
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}
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try cg.genSetReg(val_reg, val_ty, ptr.tracking(cg).short.deref(), .{});
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},
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.load_frame => |val_frame_addr| {
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var val_ptr = try cg.tempFromValue(.usize, .{ .lea_frame = val_frame_addr });
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var len = try cg.tempFromValue(.usize, .{ .immediate = val_abi_size });
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var len = try cg.tempFromValue(.usize, .{ .immediate = val_ty.abiSize(cg.pt.zcu) });
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try val_ptr.memcpy(ptr, &len, cg);
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try val_ptr.die(cg);
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try len.die(cg);
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@ -27908,7 +27982,7 @@ const Temp = struct {
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);
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} else continue :val .{ .register = undefined },
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.register => {
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while (try ptr.toLea(cg) or try val.toAnyReg(cg)) {}
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while (try ptr.toLea(cg) or try val.toRegClass(true, .general_purpose, cg)) {}
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const val_reg = val.tracking(cg).short.register;
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switch (val_reg.class()) {
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.general_purpose => try cg.asmMemoryRegister(
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@ -28224,6 +28298,7 @@ const Select = struct {
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any_int,
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any_signed_int,
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any_float,
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po2_any,
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bool_vec: Memory.Size,
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vec: Memory.Size,
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signed_int_vec: Memory.Size,
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@ -28250,15 +28325,17 @@ const Select = struct {
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unsigned_or_exact_remainder_int: struct { of: Memory.Size, is: Memory.Size },
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signed_int: Memory.Size,
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unsigned_int: Memory.Size,
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elem_int: Memory.Size,
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fn accepts(constraint: Constraint, ty: Type, cg: *CodeGen) bool {
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const zcu = cg.pt.zcu;
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switch (constraint) {
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.any => return true,
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.any_bool_vec => return ty.isVector(zcu) and ty.scalarType(zcu).toIntern() == .bool_type,
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.any_bool_vec => return ty.isVector(zcu) and ty.childType(zcu).toIntern() == .bool_type,
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.any_int => return ty.toIntern() == .bool_type or ty.isPtrAtRuntime(zcu) or ty.isAbiInt(zcu),
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.any_signed_int => return ty.isAbiInt(zcu) and ty.intInfo(zcu).signedness == .signed,
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.any_float => return ty.scalarType(zcu).isRuntimeFloat(),
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.any_float => return ty.isRuntimeFloat(),
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.po2_any => return std.math.isPowerOfTwo(ty.abiSize(zcu)),
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.bool_vec => |size| return ty.isVector(zcu) and ty.scalarType(zcu).toIntern() == .bool_type and
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size.bitSize(cg.target) >= ty.vectorLen(zcu),
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.vec => |size| return ty.isVector(zcu) and ty.scalarType(zcu).toIntern() != .bool_type and
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@ -28434,6 +28511,12 @@ const Select = struct {
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const int_info = ty.intInfo(zcu);
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return int_info.signedness == .unsigned and size.bitSize(cg.target) >= int_info.bits;
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},
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.elem_int => |size| {
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const elem_ty = ty.childType(zcu);
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if (elem_ty.toIntern() == .bool_type) return true;
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if (elem_ty.isPtrAtRuntime(zcu)) return size.bitSize(cg.target) >= cg.target.ptrBitWidth();
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return elem_ty.isAbiInt(zcu) and size.bitSize(cg.target) >= elem_ty.intInfo(zcu).bits;
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},
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}
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}
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};
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@ -29107,7 +29190,14 @@ const Select = struct {
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const UnsignedImm = @Type(.{
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.int = .{ .signedness = .unsigned, .bits = @typeInfo(SignedImm).int.bits },
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});
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return op.imm + @as(i5, op.adjust.factor) * op.adjust.scale.toFactor() * @as(SignedImm, switch (op.adjust.amount) {
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return switch (op.index.ref) {
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else => |ref| switch (ref.deref(s).tracking(s.cg).short) {
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else => unreachable,
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.immediate => |imm| op.index.scale.toFactor() * @as(i32, @intCast(imm)),
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.register => 0,
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},
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.none => 0,
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} + @as(i5, op.adjust.factor) * op.adjust.scale.toFactor() * @as(SignedImm, switch (op.adjust.amount) {
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.none => 0,
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.ptr_size => @divExact(s.cg.target.ptrBitWidth(), 8),
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.ptr_bit_size => s.cg.target.ptrBitWidth(),
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@ -29120,7 +29210,7 @@ const Select = struct {
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op.base.ref.deref(s).typeOf(s.cg).scalarType(s.cg.pt.zcu).abiSize(s.cg.pt.zcu),
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@divExact(op.base.size.bitSize(s.cg.target), 8),
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)),
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.src0_elem_size => @intCast(Select.Operand.Ref.src0.deref(s).typeOf(s.cg).scalarType(s.cg.pt.zcu).abiSize(s.cg.pt.zcu)),
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.src0_elem_size => @intCast(Select.Operand.Ref.src0.deref(s).typeOf(s.cg).childType(s.cg.pt.zcu).abiSize(s.cg.pt.zcu)),
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.smin => @as(SignedImm, std.math.minInt(SignedImm)) >> @truncate(
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-%op.base.ref.deref(s).typeOf(s.cg).scalarType(s.cg.pt.zcu).bitSize(s.cg.pt.zcu),
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),
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@ -29130,7 +29220,7 @@ const Select = struct {
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.umax => @bitCast(@as(UnsignedImm, std.math.maxInt(UnsignedImm)) >> @truncate(
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-%op.base.ref.deref(s).typeOf(s.cg).scalarType(s.cg.pt.zcu).bitSize(s.cg.pt.zcu),
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)),
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});
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}) + op.imm;
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}
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fn lower(op: Select.Operand, s: *Select) !CodeGen.Operand {
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@ -29160,7 +29250,11 @@ const Select = struct {
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.mod = .{ .rm = .{
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.size = op.base.size,
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.index = switch (op.index.ref) {
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else => |ref| registerAlias(ref.deref(s).tracking(s.cg).short.register, @divExact(s.cg.target.ptrBitWidth(), 8)),
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else => |ref| switch (ref.deref(s).tracking(s.cg).short) {
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else => unreachable,
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.immediate => .none,
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.register => |index_reg| registerAlias(index_reg, @divExact(s.cg.target.ptrBitWidth(), 8)),
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},
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.none => .none,
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},
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.scale = op.index.scale,
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@ -29170,7 +29264,11 @@ const Select = struct {
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.mem => .{ .mem = try op.base.ref.deref(s).tracking(s.cg).short.mem(s.cg, .{
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.size = op.base.size,
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.index = switch (op.index.ref) {
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else => |ref| registerAlias(ref.deref(s).tracking(s.cg).short.register, @divExact(s.cg.target.ptrBitWidth(), 8)),
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else => |ref| switch (ref.deref(s).tracking(s.cg).short) {
|
||||
else => unreachable,
|
||||
.immediate => .none,
|
||||
.register => |index_reg| registerAlias(index_reg, @divExact(s.cg.target.ptrBitWidth(), 8)),
|
||||
},
|
||||
.none => .none,
|
||||
},
|
||||
.scale = op.index.scale,
|
||||
|
||||
@ -5,4 +5,5 @@ test {
|
||||
if (builtin.zig_backend != .stage2_x86_64) return error.SkipZigTest;
|
||||
if (builtin.object_format == .coff) return error.SkipZigTest;
|
||||
_ = @import("x86_64/math.zig");
|
||||
_ = @import("x86_64/mem.zig");
|
||||
}
|
||||
|
||||
@ -88,6 +88,7 @@ pub fn build(b: *std.Build) void {
|
||||
const cpu = query.serializeCpuAlloc(b.allocator) catch @panic("OOM");
|
||||
for ([_][]const u8{
|
||||
"math.zig",
|
||||
"mem.zig",
|
||||
}) |path| {
|
||||
const test_mod = b.createModule(.{
|
||||
.root_source_file = b.path(path),
|
||||
|
||||
31
test/behavior/x86_64/mem.zig
Normal file
31
test/behavior/x86_64/mem.zig
Normal file
@ -0,0 +1,31 @@
|
||||
fn access(comptime array: anytype) !void {
|
||||
var slice: []const @typeInfo(@TypeOf(array)).array.child = undefined;
|
||||
slice = &array;
|
||||
inline for (0.., &array) |ct_index, *elem| {
|
||||
var rt_index: usize = undefined;
|
||||
rt_index = ct_index;
|
||||
if (&slice.ptr[ct_index] != elem) return error.Unexpected;
|
||||
if (&slice[ct_index] != elem) return error.Unexpected;
|
||||
if (&slice.ptr[rt_index] != elem) return error.Unexpected;
|
||||
if (&slice[rt_index] != elem) return error.Unexpected;
|
||||
if (slice.ptr[ct_index] != elem.*) return error.Unexpected;
|
||||
if (slice[ct_index] != elem.*) return error.Unexpected;
|
||||
if (slice.ptr[rt_index] != elem.*) return error.Unexpected;
|
||||
if (slice[rt_index] != elem.*) return error.Unexpected;
|
||||
}
|
||||
}
|
||||
test access {
|
||||
try access([3]u8{ 0xdb, 0xef, 0xbd });
|
||||
try access([3]u16{ 0x340e, 0x3654, 0x88d7 });
|
||||
try access([3]u32{ 0xd424c2c0, 0x2d6ac466, 0x5a0cfaba });
|
||||
try access([3]u64{
|
||||
0x9327a4f5221666a6,
|
||||
0x5c34d3ddd84a8b12,
|
||||
0xbae087f39f649260,
|
||||
});
|
||||
try access([3]u128{
|
||||
0x601cf010065444d4d42d5536dd9b95db,
|
||||
0xa03f592fcaa22d40af23a0c735531e3c,
|
||||
0x5da44907b31602b95c2d93f0b582ceab,
|
||||
});
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user