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https://github.com/ziglang/zig.git
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stage2 ARM: start adding more instructions, return values, parameters
This commit is contained in:
joachimschmidt557
parent
e9434ff8f4
commit
0a54f04dbc
119
src/codegen.zig
119
src/codegen.zig
@ -1461,7 +1461,35 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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}
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},
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.arm => {
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if (info.args.len > 0) return self.fail(inst.base.src, "TODO implement fn args for {}", .{self.target.cpu.arch});
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for (info.args) |mc_arg, arg_i| {
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const arg = inst.args[arg_i];
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const arg_mcv = try self.resolveInst(inst.args[arg_i]);
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switch (mc_arg) {
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.none => continue,
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.undef => unreachable,
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.immediate => unreachable,
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.unreach => unreachable,
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.dead => unreachable,
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.embedded_in_code => unreachable,
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.memory => unreachable,
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.compare_flags_signed => unreachable,
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.compare_flags_unsigned => unreachable,
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.register => |reg| {
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try self.genSetReg(arg.src, reg, arg_mcv);
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// TODO interact with the register allocator to mark the instruction as moved.
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},
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.stack_offset => {
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return self.fail(inst.base.src, "TODO implement calling with parameters in memory", .{});
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},
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.ptr_stack_offset => {
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return self.fail(inst.base.src, "TODO implement calling with MCValue.ptr_stack_offset arg", .{});
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},
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.ptr_embedded_in_code => {
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return self.fail(inst.base.src, "TODO implement calling with MCValue.ptr_embedded_in_code arg", .{});
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},
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}
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}
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if (inst.func.cast(ir.Inst.Constant)) |func_inst| {
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if (func_inst.val.cast(Value.Payload.Function)) |func_val| {
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@ -1482,7 +1510,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// of course. Add pushing lr to stack
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// and popping after call
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try self.genSetReg(inst.base.src, .lr, .{ .memory = got_addr });
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
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if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
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} else {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .lr, Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bx(.al, .lr).toU32());
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}
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} else {
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return self.fail(inst.base.src, "TODO implement calling bitcasted functions", .{});
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}
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@ -2213,14 +2247,14 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// least amount of necessary instructions (use
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// more intelligent rotating)
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if (x <= math.maxInt(u8)) {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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return;
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} else if (x <= math.maxInt(u16)) {
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// TODO Use movw Note: Not supported on
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// all ARM targets!
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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} else if (x <= math.maxInt(u32)) {
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// TODO Use movw and movt Note: Not
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// supported on all ARM targets! Also TODO
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@ -2232,15 +2266,23 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// orr reg, reg, #0xbb, 24
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// orr reg, reg, #0xcc, 16
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// orr reg, reg, #0xdd, 8
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
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return;
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} else {
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return self.fail(src, "ARM registers are 32-bit wide", .{});
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}
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},
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.register => |src_reg| {
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// If the registers are the same, nothing to do.
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if (src_reg.id() == reg.id())
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return;
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// mov reg, src_reg
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.reg(src_reg, Instruction.Operand.Shift.none)).toU32());
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},
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.memory => |addr| {
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// The value is in memory at a hard-coded address.
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// If the type is a pointer, it means the pointer address is at this memory location.
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@ -2701,6 +2743,53 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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else => return self.fail(src, "TODO implement function parameters for {} on x86_64", .{cc}),
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}
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},
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.arm => {
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switch (cc) {
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.Naked => {
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assert(result.args.len == 0);
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result.return_value = .{ .unreach = {} };
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result.stack_byte_count = 0;
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result.stack_align = 1;
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return result;
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},
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.Unspecified, .C => {
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// ARM Procedure Call Standard, Chapter 6.5
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var ncrn: usize = 0; // Next Core Register Number
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var nsaa: u32 = 0; // Next stacked argument address
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for (param_types) |ty, i| {
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if (ty.abiAlignment(self.target.*) == 8) {
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// Round up NCRN to the next even number
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ncrn += ncrn % 2;
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}
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const param_size = @intCast(u32, ty.abiSize(self.target.*));
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if (std.math.divCeil(u32, param_size, 4) catch unreachable <= 4 - ncrn) {
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if (param_size <= 4) {
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result.args[i] = .{ .register = c_abi_int_param_regs[ncrn] };
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ncrn += 1;
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} else {
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return self.fail(src, "TODO MCValues with multiple registers", .{});
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}
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} else {
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ncrn = 4;
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if (ty.abiAlignment(self.target.*) == 8) {
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if (nsaa % 8 != 0) {
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nsaa += 8 - (nsaa % 8);
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}
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}
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result.args[i] = .{ .stack_offset = nsaa };
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nsaa += param_size;
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}
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}
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result.stack_byte_count = nsaa;
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result.stack_align = 4;
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},
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else => return self.fail(src, "TODO implement function parameters for {} on arm", .{cc}),
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}
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},
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else => if (param_types.len != 0)
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return self.fail(src, "TODO implement codegen parameters for {}", .{self.target.cpu.arch}),
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}
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@ -2719,6 +2808,18 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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},
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else => return self.fail(src, "TODO implement function return values for {}", .{cc}),
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},
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.arm => switch (cc) {
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.Naked => unreachable,
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.Unspecified, .C => {
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const ret_ty_size = @intCast(u32, ret_ty.abiSize(self.target.*));
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if (ret_ty_size <= 4) {
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result.return_value = .{ .register = c_abi_int_return_regs[0] };
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} else {
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return self.fail(src, "TODO support more return types for ARM backend", .{});
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}
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},
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else => return self.fail(src, "TODO implement function return values for {}", .{cc}),
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},
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else => return self.fail(src, "TODO implement codegen return values for {}", .{self.target.cpu.arch}),
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}
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return result;
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@ -113,6 +113,13 @@ test "Register.id" {
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testing.expectEqual(@as(u4, 15), Register.pc.id());
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}
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/// Program status registers containing flags, mode bits and other
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/// vital information
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pub const Psr = enum {
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cpsr,
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spsr,
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};
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pub const callee_preserved_regs = [_]Register{ .r0, .r1, .r2, .r3, .r4, .r5, .r6, .r7, .r8, .r10 };
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pub const c_abi_int_param_regs = [_]Register{ .r0, .r1, .r2, .r3 };
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pub const c_abi_int_return_regs = [_]Register{ .r0, .r1 };
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@ -135,15 +142,26 @@ pub const Instruction = union(enum) {
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offset: u12,
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rd: u4,
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rn: u4,
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l: u1,
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w: u1,
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b: u1,
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u: u1,
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p: u1,
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i: u1,
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load_store: u1,
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write_back: u1,
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byte_word: u1,
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up_down: u1,
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pre_post: u1,
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imm: u1,
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fixed: u2 = 0b01,
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cond: u4,
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},
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BlockDataTransfer: packed struct {
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register_list: u16,
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rn: u4,
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load_store: u1,
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write_back: u1,
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psr_or_user: u1,
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up_down: u1,
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pre_post: u1,
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fixed: u3 = 0b100,
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cond: u4,
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},
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Branch: packed struct {
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offset: u24,
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link: u1,
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@ -235,14 +253,14 @@ pub const Instruction = union(enum) {
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rs: u4,
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},
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const Type = enum(u2) {
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LogicalLeft,
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LogicalRight,
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ArithmeticRight,
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RotateRight,
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pub const Type = enum(u2) {
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logical_left,
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logical_right,
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arithmetic_right,
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rotate_right,
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};
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const none = Shift{
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pub const none = Shift{
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.Immediate = .{
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.amount = 0,
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.typ = 0,
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@ -338,10 +356,32 @@ pub const Instruction = union(enum) {
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}
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};
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/// Represents the register list operand to a block data transfer
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/// instruction
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pub const RegisterList = packed struct {
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r0: bool = false,
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r1: bool = false,
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r2: bool = false,
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r3: bool = false,
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r4: bool = false,
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r5: bool = false,
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r6: bool = false,
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r7: bool = false,
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r8: bool = false,
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r9: bool = false,
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r10: bool = false,
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r11: bool = false,
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r12: bool = false,
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r13: bool = false,
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r14: bool = false,
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r15: bool = false,
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};
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.DataProcessing => |v| @bitCast(u32, v),
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.SingleDataTransfer => |v| @bitCast(u32, v),
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.BlockDataTransfer => |v| @bitCast(u32, v),
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.Branch => |v| @bitCast(u32, v),
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.BranchExchange => |v| @bitCast(u32, v),
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.SupervisorCall => |v| @bitCast(u32, v),
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@ -380,7 +420,7 @@ pub const Instruction = union(enum) {
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pre_post: u1,
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up_down: u1,
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byte_word: u1,
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writeback: u1,
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write_back: u1,
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load_store: u1,
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) Instruction {
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return Instruction{
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@ -389,12 +429,36 @@ pub const Instruction = union(enum) {
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.rn = rn.id(),
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.rd = rd.id(),
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.offset = offset.toU12(),
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.l = load_store,
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.w = writeback,
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.b = byte_word,
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.u = up_down,
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.p = pre_post,
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.i = if (offset == .Immediate) 0 else 1,
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.load_store = load_store,
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.write_back = write_back,
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.byte_word = byte_word,
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.up_down = up_down,
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.pre_post = pre_post,
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.imm = if (offset == .Immediate) 0 else 1,
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},
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};
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}
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fn blockDataTransfer(
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cond: Condition,
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rn: Register,
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reg_list: RegisterList,
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pre_post: u1,
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up_down: u1,
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psr_or_user: u1,
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write_back: u1,
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load_store: u1,
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) Instruction {
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return Instruction{
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.BlockDataTransfer = .{
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.register_list = @bitCast(u16, reg_list),
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.rn = rn.id(),
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.load_store = load_store,
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.write_back = write_back,
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.psr_or_user = psr_or_user,
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.up_down = up_down,
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.pre_post = pre_post,
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.cond = @enumToInt(cond),
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},
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};
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}
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@ -442,36 +506,68 @@ pub const Instruction = union(enum) {
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// Data processing
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pub fn @"and"(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .@"and", s, rd, rn, op2);
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pub fn @"and"(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .@"and", 0, rd, rn, op2);
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}
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pub fn eor(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .eor, s, rd, rn, op2);
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pub fn ands(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .@"and", 1, rd, rn, op2);
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}
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pub fn sub(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .sub, s, rd, rn, op2);
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pub fn eor(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .eor, 0, rd, rn, op2);
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}
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pub fn rsb(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .rsb, s, rd, rn, op2);
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pub fn eors(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .eor, 1, rd, rn, op2);
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}
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pub fn add(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .add, s, rd, rn, op2);
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pub fn sub(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .sub, 0, rd, rn, op2);
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}
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pub fn adc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .adc, s, rd, rn, op2);
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pub fn subs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .sub, 1, rd, rn, op2);
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}
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pub fn sbc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .sbc, s, rd, rn, op2);
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pub fn rsb(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .rsb, 0, rd, rn, op2);
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}
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pub fn rsc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .rsc, s, rd, rn, op2);
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pub fn rsbs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .rsb, 1, rd, rn, op2);
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}
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pub fn add(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .add, 0, rd, rn, op2);
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}
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pub fn adds(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .add, 1, rd, rn, op2);
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}
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pub fn adc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .adc, 0, rd, rn, op2);
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}
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pub fn adcs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
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return dataProcessing(cond, .adc, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn sbc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sbc, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn sbcs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sbc, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn rsc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsc, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn rscs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsc, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn tst(cond: Condition, rn: Register, op2: Operand) Instruction {
|
||||
@ -490,20 +586,42 @@ pub const Instruction = union(enum) {
|
||||
return dataProcessing(cond, .cmn, 1, .r0, rn, op2);
|
||||
}
|
||||
|
||||
pub fn orr(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .orr, s, rd, rn, op2);
|
||||
pub fn orr(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .orr, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn mov(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mov, s, rd, .r0, op2);
|
||||
pub fn orrs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .orr, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn bic(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .bic, s, rd, rn, op2);
|
||||
pub fn mov(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mov, 0, rd, .r0, op2);
|
||||
}
|
||||
|
||||
pub fn mvn(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mvn, s, rd, .r0, op2);
|
||||
pub fn movs(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mov, 1, rd, .r0, op2);
|
||||
}
|
||||
|
||||
pub fn bic(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .bic, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn bics(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .bic, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn mvn(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mvn, 0, rd, .r0, op2);
|
||||
}
|
||||
|
||||
pub fn mvns(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mvn, 1, rd, .r0, op2);
|
||||
}
|
||||
|
||||
// PSR transfer
|
||||
|
||||
pub fn mrs(cond: Condition, rd: Register, psr: Psr) Instruction {
|
||||
return dataProcessing(cond, if (psr == .cpsr) .tst else .cmp, 0, rd, .r15, Operand.reg(.r0, Operand.Shift.none));
|
||||
}
|
||||
|
||||
// Single data transfer
|
||||
@ -512,10 +630,28 @@ pub const Instruction = union(enum) {
|
||||
return singleDataTransfer(cond, rd, rn, offset, 1, 1, 0, 0, 1);
|
||||
}
|
||||
|
||||
pub fn ldrb(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, offset, 1, 1, 1, 0, 1);
|
||||
}
|
||||
|
||||
pub fn str(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, offset, 1, 1, 0, 0, 0);
|
||||
}
|
||||
|
||||
pub fn strb(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, offset, 1, 1, 1, 0, 0);
|
||||
}
|
||||
|
||||
// Block data transfer
|
||||
|
||||
pub fn ldm(cond: Condition, rn: Register, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 1, 0, 0, 0, 1);
|
||||
}
|
||||
|
||||
pub fn stm(cond: Condition, rn: Register, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 1, 0, 0, 0, 0);
|
||||
}
|
||||
|
||||
// Branch
|
||||
|
||||
pub fn b(cond: Condition, offset: i24) Instruction {
|
||||
@ -559,17 +695,21 @@ test "serialize instructions" {
|
||||
|
||||
const testcases = [_]Testcase{
|
||||
.{ // add r0, r0, r0
|
||||
.inst = Instruction.add(.al, 0, .r0, .r0, Instruction.Operand.reg(.r0, Instruction.Operand.Shift.none)),
|
||||
.inst = Instruction.add(.al, .r0, .r0, Instruction.Operand.reg(.r0, Instruction.Operand.Shift.none)),
|
||||
.expected = 0b1110_00_0_0100_0_0000_0000_00000000_0000,
|
||||
},
|
||||
.{ // mov r4, r2
|
||||
.inst = Instruction.mov(.al, 0, .r4, Instruction.Operand.reg(.r2, Instruction.Operand.Shift.none)),
|
||||
.inst = Instruction.mov(.al, .r4, Instruction.Operand.reg(.r2, Instruction.Operand.Shift.none)),
|
||||
.expected = 0b1110_00_0_1101_0_0000_0100_00000000_0010,
|
||||
},
|
||||
.{ // mov r0, #42
|
||||
.inst = Instruction.mov(.al, 0, .r0, Instruction.Operand.imm(42, 0)),
|
||||
.inst = Instruction.mov(.al, .r0, Instruction.Operand.imm(42, 0)),
|
||||
.expected = 0b1110_00_1_1101_0_0000_0000_0000_00101010,
|
||||
},
|
||||
.{ // mrs r5, cpsr
|
||||
.inst = Instruction.mrs(.al, .r5, .cpsr),
|
||||
.expected = 0b1110_00010_0_001111_0101_000000000000,
|
||||
},
|
||||
.{ // ldr r0, [r2, #42]
|
||||
.inst = Instruction.ldr(.al, .r0, .r2, Instruction.Offset.imm(42)),
|
||||
.expected = 0b1110_01_0_1_1_0_0_1_0010_0000_000000101010,
|
||||
@ -598,6 +738,10 @@ test "serialize instructions" {
|
||||
.inst = Instruction.bkpt(42),
|
||||
.expected = 0b1110_0001_0010_000000000010_0111_1010,
|
||||
},
|
||||
.{ // stmfd r9, {r0}
|
||||
.inst = Instruction.stm(.al, .r9, .{ .r0 = true }),
|
||||
.expected = 0b1110_100_1_0_0_0_0_1001_0000000000000001,
|
||||
},
|
||||
};
|
||||
|
||||
for (testcases) |case| {
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user