From 08154c0deb653e016d6eb285c85094048eeded89 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Mon, 13 Jul 2020 00:28:11 -0700 Subject: [PATCH] stage2: add retvoid support to CBE --- src-self-hosted/Module.zig | 5 +++-- src-self-hosted/{cgen.zig => codegen/c.zig} | 15 ++++++++------- src-self-hosted/link.zig | 4 ++-- test/stage2/cbe.zig | 1 + 4 files changed, 14 insertions(+), 11 deletions(-) rename src-self-hosted/{cgen.zig => codegen/c.zig} (95%) diff --git a/src-self-hosted/Module.zig b/src-self-hosted/Module.zig index 03307ab96d..975158c477 100644 --- a/src-self-hosted/Module.zig +++ b/src-self-hosted/Module.zig @@ -1210,8 +1210,9 @@ fn astGenAndAnalyzeDecl(self: *Module, decl: *Decl) !bool { try self.astGenBlock(&gen_scope.base, body_block); - const last_inst = gen_scope.instructions.items[gen_scope.instructions.items.len - 1]; - if (!last_inst.tag.isNoReturn()) { + if (!fn_type.fnReturnType().isNoReturn() and (gen_scope.instructions.items.len == 0 or + !gen_scope.instructions.items[gen_scope.instructions.items.len - 1].tag.isNoReturn())) + { const src = tree.token_locs[body_block.rbrace].start; _ = try self.addZIRInst(&gen_scope.base, src, zir.Inst.ReturnVoid, .{}, .{}); } diff --git a/src-self-hosted/cgen.zig b/src-self-hosted/codegen/c.zig similarity index 95% rename from src-self-hosted/cgen.zig rename to src-self-hosted/codegen/c.zig index 91dc4a81a4..ebc4ff7e1a 100644 --- a/src-self-hosted/cgen.zig +++ b/src-self-hosted/codegen/c.zig @@ -1,11 +1,11 @@ -const link = @import("link.zig"); -const Module = @import("Module.zig"); - const std = @import("std"); -const Inst = @import("ir.zig").Inst; -const Value = @import("value.zig").Value; -const Type = @import("type.zig").Type; +const link = @import("../link.zig"); +const Module = @import("../Module.zig"); + +const Inst = @import("../ir.zig").Inst; +const Value = @import("../value.zig").Value; +const Type = @import("../type.zig").Type; const C = link.File.C; const Decl = Module.Decl; @@ -95,7 +95,8 @@ fn genFn(file: *C, decl: *Decl) !void { .assembly => try genAsm(file, inst.cast(Inst.Assembly).?, decl), .call => try genCall(file, inst.cast(Inst.Call).?, decl), .ret => try genRet(file, inst.cast(Inst.Ret).?, decl, tv.ty.fnReturnType()), - else => |e| return file.fail(decl.src(), "TODO {}", .{e}), + .retvoid => try file.main.writer().print("return;", .{}), + else => |e| return file.fail(decl.src(), "TODO implement C codegen for {}", .{e}), } } try writer.writeAll("\n"); diff --git a/src-self-hosted/link.zig b/src-self-hosted/link.zig index 64328d4df5..776f6de31c 100644 --- a/src-self-hosted/link.zig +++ b/src-self-hosted/link.zig @@ -7,7 +7,7 @@ const Module = @import("Module.zig"); const fs = std.fs; const elf = std.elf; const codegen = @import("codegen.zig"); -const cgen = @import("cgen.zig"); +const c_codegen = @import("codegen/c.zig"); const default_entry_addr = 0x8000000; @@ -259,7 +259,7 @@ pub const File = struct { } pub fn updateDecl(self: *File.C, module: *Module, decl: *Module.Decl) !void { - cgen.generate(self, decl) catch |err| { + c_codegen.generate(self, decl) catch |err| { if (err == error.CGenFailure) { try module.failed_decls.put(module.gpa, decl, self.error_msg); } diff --git a/test/stage2/cbe.zig b/test/stage2/cbe.zig index e642489b01..e817029b83 100644 --- a/test/stage2/cbe.zig +++ b/test/stage2/cbe.zig @@ -62,6 +62,7 @@ pub fn addCases(ctx: *TestContext) !void { \\ register size_t rax_constant __asm__("rax") = 231; \\ register size_t rdi_constant __asm__("rdi") = 0; \\ __asm volatile ("syscall" :: ""(rax_constant), ""(rdi_constant)); + \\ return; \\} \\ );