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llvm: Disable the machine outliner pass on RISC-V

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Alex Rønne Petersen 2025-06-30 07:01:35 +02:00
parent aa7b32d781
commit 07114e6bc6
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4 changed files with 15 additions and 6 deletions
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3
src/codegen/llvm.zig
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@ -1068,6 +1068,9 @@ pub const Object = struct {
.full => .FullPreLink,
},
.allow_fast_isel = true,
// LLVM's RISC-V backend for some reason enables the machine outliner by default even
// though it's clearly not ready and produces multiple miscompilations in our std tests.
.allow_machine_outliner = !comp.root_mod.resolved_target.result.cpu.arch.isRISCV(),
.asm_filename = null,
.bin_filename = options.bin_path,
.llvm_ir_filename = options.post_ir_path,

1
src/codegen/llvm/bindings.zig
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@ -92,6 +92,7 @@ pub const TargetMachine = opaque {
sancov: bool,
lto: LtoPhase,
allow_fast_isel: bool,
allow_machine_outliner: bool,
asm_filename: ?[*:0]const u8,
bin_filename: ?[*:0]const u8,
llvm_ir_filename: ?[*:0]const u8,

16
src/zig_llvm.cpp
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@ -260,6 +260,16 @@ ZIG_EXTERN_C bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machi
TargetMachine &target_machine = *reinterpret_cast<TargetMachine*>(targ_machine_ref);
if (options->allow_fast_isel) {
target_machine.setO0WantsFastISel(true);
} else {
target_machine.setFastISel(false);
}
if (!options->allow_machine_outliner) {
target_machine.setMachineOutliner(false);
}
Module &llvm_module = *unwrap(module_ref);
// Pipeline configurations
@ -385,12 +395,6 @@ ZIG_EXTERN_C bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machi
}
}
if (options->allow_fast_isel) {
target_machine.setO0WantsFastISel(true);
} else {
target_machine.setFastISel(false);
}
// Optimization phase
module_pm.run(llvm_module, module_am);

1
src/zig_llvm.h
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@ -71,6 +71,7 @@ struct ZigLLVMEmitOptions {
bool sancov;
ZigLLVMThinOrFullLTOPhase lto;
bool allow_fast_isel;
bool allow_machine_outliner;
const char *asm_filename;
const char *bin_filename;
const char *llvm_ir_filename;