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stage2 ARM: optimize airSliceElemVal for elem_size 1 or 4
In these cases, the AIR inst can be lowered to only one ldr instruction. Also fixes shifts in arm.bits.Offset
This commit is contained in:
joachimschmidt557
Jakub Konka
parent
71321b6941
commit
04f379dd41
@ -1222,9 +1222,16 @@ fn airPtrSlicePtrPtr(self: *Self, inst: Air.Inst.Index) !void {
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fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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const is_volatile = false; // TODO
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (!is_volatile and self.liveness.isUnused(inst)) .dead else result: {
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if (!is_volatile and self.liveness.isUnused(inst)) return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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const result: MCValue = result: {
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const slice_mcv = try self.resolveInst(bin_op.lhs);
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// TODO optimize for the case where the index is a constant,
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// i.e. index_mcv == .immediate
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const index_mcv = try self.resolveInst(bin_op.rhs);
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const index_is_register = index_mcv == .register;
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const slice_ty = self.air.typeOf(bin_op.lhs);
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const elem_ty = slice_ty.childType();
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const elem_size = elem_ty.abiSize(self.target.*);
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@ -1232,12 +1239,8 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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var buf: Type.SlicePtrFieldTypeBuffer = undefined;
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const slice_ptr_field_type = slice_ty.slicePtrFieldType(&buf);
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// TODO optimize this for the case when elem_size is a power
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// of two (includes elem_size == 1)
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const offset_mcv = try self.genArmMulConstant(inst, bin_op.rhs, 1, @intCast(u32, elem_size));
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assert(offset_mcv == .register); // result of multiplication should always be register
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self.register_manager.freezeRegs(&.{offset_mcv.register});
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defer self.register_manager.unfreezeRegs(&.{offset_mcv.register});
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if (index_is_register) self.register_manager.freezeRegs(&.{index_mcv.register});
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defer if (index_is_register) self.register_manager.unfreezeRegs(&.{index_mcv.register});
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const base_mcv: MCValue = switch (slice_mcv) {
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.stack_offset => .{ .register = try self.copyToTmpRegister(slice_ptr_field_type, slice_mcv) },
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@ -1246,61 +1249,67 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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self.register_manager.freezeRegs(&.{base_mcv.register});
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defer self.register_manager.unfreezeRegs(&.{base_mcv.register});
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if (elem_size <= 4) {
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const dst_reg = try self.register_manager.allocReg(inst);
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self.register_manager.freezeRegs(&.{dst_reg});
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defer self.register_manager.unfreezeRegs(&.{dst_reg});
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switch (elem_size) {
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1, 4 => {
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const dst_reg = try self.register_manager.allocReg(inst);
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const dst_mcv = MCValue{ .register = dst_reg };
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self.register_manager.freezeRegs(&.{dst_reg});
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defer self.register_manager.unfreezeRegs(&.{dst_reg});
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switch (elem_size) {
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1, 4 => {
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const tag: Mir.Inst.Tag = switch (elem_size) {
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1 => .ldrb,
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4 => .ldr,
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else => unreachable,
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};
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const index_reg: Register = switch (index_mcv) {
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.register => |reg| reg,
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else => try self.copyToTmpRegister(Type.usize, index_mcv),
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};
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self.register_manager.freezeRegs(&.{index_reg});
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defer self.register_manager.unfreezeRegs(&.{index_reg});
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_ = try self.addInst(.{
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.tag = tag,
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.data = .{ .rr_offset = .{
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.rt = dst_reg,
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.rn = base_mcv.register,
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.offset = .{ .offset = Instruction.Offset.reg(offset_mcv.register, 0) },
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} },
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});
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},
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2 => {
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_ = try self.addInst(.{
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.tag = .ldrh,
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.data = .{ .rr_extra_offset = .{
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.rt = dst_reg,
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.rn = base_mcv.register,
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.offset = .{ .offset = Instruction.ExtraLoadStoreOffset.reg(offset_mcv.register) },
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} },
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});
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},
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else => unreachable,
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}
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const tag: Mir.Inst.Tag = switch (elem_size) {
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1 => .ldrb,
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4 => .ldr,
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else => unreachable,
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};
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const shift: u5 = switch (elem_size) {
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1 => 0,
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4 => 2,
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else => unreachable,
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};
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break :result MCValue{ .register = dst_reg };
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} else {
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const dst_mcv = try self.allocRegOrMem(inst, false);
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_ = try self.addInst(.{
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.tag = tag,
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.data = .{ .rr_offset = .{
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.rt = dst_reg,
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.rn = base_mcv.register,
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.offset = .{ .offset = Instruction.Offset.reg(index_reg, .{ .lsl = shift }) },
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} },
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});
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const addr_reg = try self.register_manager.allocReg(null);
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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break :result dst_mcv;
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},
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else => {
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const dst_mcv = try self.allocRegOrMem(inst, true);
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try self.genArmBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);
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const offset_mcv = try self.genArmMulConstant(bin_op.rhs, @intCast(u32, elem_size));
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assert(offset_mcv == .register); // result of multiplication should always be register
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self.register_manager.freezeRegs(&.{offset_mcv.register});
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defer self.register_manager.unfreezeRegs(&.{offset_mcv.register});
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// I know we will unfreeze these registers at the end of
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// the scope of :result. However, at this point in time,
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// neither the base register nor the offset register
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// contains any valuable data anymore. In order to reduce
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// register pressure, unfreeze them prematurely
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self.register_manager.unfreezeRegs(&.{ base_mcv.register, offset_mcv.register });
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const addr_reg = try self.register_manager.allocReg(null);
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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try self.load(dst_mcv, .{ .register = addr_reg }, slice_ptr_field_type);
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try self.genArmBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);
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break :result dst_mcv;
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// I know we will unfreeze these registers at the end of
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// the scope of :result. However, at this point in time,
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// neither the base register nor the offset register
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// contains any valuable data anymore. In order to reduce
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// register pressure, unfreeze them prematurely
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self.register_manager.unfreezeRegs(&.{ base_mcv.register, offset_mcv.register });
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try self.load(dst_mcv, .{ .register = addr_reg }, slice_ptr_field_type);
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break :result dst_mcv;
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},
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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@ -1931,8 +1940,8 @@ fn genArmBinOpCode(
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.shl, .shr => {
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assert(!swap_lhs_and_rhs);
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const shift_amount = switch (operand) {
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.Register => |reg_op| Instruction.ShiftAmount.reg(@intToEnum(Register, reg_op.rm)),
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.Immediate => |imm_op| Instruction.ShiftAmount.imm(@intCast(u5, imm_op.imm)),
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.register => |reg_op| Instruction.ShiftAmount.reg(@intToEnum(Register, reg_op.rm)),
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.immediate => |imm_op| Instruction.ShiftAmount.imm(@intCast(u5, imm_op.imm)),
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};
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const tag: Mir.Inst.Tag = switch (op) {
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@ -2036,12 +2045,11 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai
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return dst_mcv;
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}
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fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_index: Liveness.OperandInt, imm: u32) !MCValue {
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fn genArmMulConstant(self: *Self, op: Air.Inst.Ref, imm: u32) !MCValue {
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const lhs = try self.resolveInst(op);
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const rhs = MCValue{ .immediate = imm };
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const lhs_is_register = lhs == .register;
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const reuse_lhs = lhs_is_register and self.reuseOperand(inst, op, op_index, lhs);
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if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
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defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
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@ -2054,23 +2062,17 @@ fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_ind
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var rhs_mcv: MCValue = rhs;
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// Allocate registers for operands and/or destination
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if (reuse_lhs) {
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// Allocate 1 register
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rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(null) };
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dst_mcv = lhs;
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// Allocate 1 or 2 registers
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if (lhs_is_register) {
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// Move RHS to register
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(null) };
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rhs_mcv = dst_mcv;
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} else {
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// Allocate 1 or 2 registers
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if (lhs_is_register) {
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// Move RHS to register
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dst_mcv = MCValue{ .register = try self.register_manager.allocReg(null) };
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rhs_mcv = dst_mcv;
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} else {
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// Move LHS and RHS to register
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const regs = try self.register_manager.allocRegs(2, .{ null, null });
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lhs_mcv = MCValue{ .register = regs[0] };
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rhs_mcv = MCValue{ .register = regs[1] };
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dst_mcv = lhs_mcv;
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}
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// Move LHS and RHS to register
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const regs = try self.register_manager.allocRegs(2, .{ null, null });
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lhs_mcv = MCValue{ .register = regs[0] };
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rhs_mcv = MCValue{ .register = regs[1] };
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dst_mcv = lhs_mcv;
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}
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// Move the operands to the newly allocated registers
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@ -2132,7 +2134,7 @@ fn genArmInlineMemcpy(
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.data = .{ .rr_offset = .{
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.rt = tmp,
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.rn = src,
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.offset = .{ .offset = Instruction.Offset.reg(count, 0) },
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.offset = .{ .offset = Instruction.Offset.reg(count, .none) },
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} },
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});
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@ -2142,7 +2144,7 @@ fn genArmInlineMemcpy(
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.data = .{ .rr_offset = .{
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.rt = tmp,
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.rn = dst,
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.offset = .{ .offset = Instruction.Offset.reg(count, 0) },
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.offset = .{ .offset = Instruction.Offset.reg(count, .none) },
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} },
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});
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@ -3126,7 +3128,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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1, 4 => {
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const offset = if (math.cast(u12, adj_off)) |imm| blk: {
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break :blk Instruction.Offset.imm(imm);
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} else |_| Instruction.Offset.reg(try self.copyToTmpRegister(Type.initTag(.u32), MCValue{ .immediate = adj_off }), 0);
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} else |_| Instruction.Offset.reg(try self.copyToTmpRegister(Type.initTag(.u32), MCValue{ .immediate = adj_off }), .none);
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const tag: Mir.Inst.Tag = switch (abi_size) {
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1 => .strb,
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@ -3450,7 +3452,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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1, 4 => {
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const offset = if (adj_off <= math.maxInt(u12)) blk: {
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break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
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} else Instruction.Offset.reg(try self.copyToTmpRegister(Type.initTag(.u32), MCValue{ .immediate = adj_off }), 0);
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} else Instruction.Offset.reg(try self.copyToTmpRegister(Type.initTag(.u32), MCValue{ .immediate = adj_off }), .none);
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const tag: Mir.Inst.Tag = switch (abi_size) {
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1 => .ldrb,
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@ -3536,7 +3538,7 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I
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1, 4 => {
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const offset = if (math.cast(u12, adj_off)) |imm| blk: {
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break :blk Instruction.Offset.imm(imm);
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} else |_| Instruction.Offset.reg(try self.copyToTmpRegister(Type.initTag(.u32), MCValue{ .immediate = adj_off }), 0);
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} else |_| Instruction.Offset.reg(try self.copyToTmpRegister(Type.initTag(.u32), MCValue{ .immediate = adj_off }), .none);
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const tag: Mir.Inst.Tag = switch (abi_size) {
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1 => .strb,
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@ -343,11 +343,11 @@ pub const Instruction = union(enum) {
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/// which can either be content from a register or an immediate
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/// value
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pub const Operand = union(enum) {
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Register: packed struct {
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register: packed struct {
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rm: u4,
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shift: u8,
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},
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Immediate: packed struct {
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immediate: packed struct {
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imm: u8,
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rotate: u4,
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},
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@ -356,12 +356,12 @@ pub const Instruction = union(enum) {
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/// register can be shifted by a specific immediate value or
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/// by the contents of another register
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pub const Shift = union(enum) {
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Immediate: packed struct {
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immediate: packed struct {
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fixed: u1 = 0b0,
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typ: u2,
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amount: u5,
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},
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Register: packed struct {
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register: packed struct {
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fixed_1: u1 = 0b1,
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typ: u2,
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fixed_2: u1 = 0b0,
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@ -376,7 +376,7 @@ pub const Instruction = union(enum) {
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};
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pub const none = Shift{
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.Immediate = .{
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.immediate = .{
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.amount = 0,
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.typ = 0,
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},
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@ -384,14 +384,14 @@ pub const Instruction = union(enum) {
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pub fn toU8(self: Shift) u8 {
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return switch (self) {
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.Register => |v| @bitCast(u8, v),
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.Immediate => |v| @bitCast(u8, v),
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.register => |v| @bitCast(u8, v),
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.immediate => |v| @bitCast(u8, v),
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};
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}
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pub fn reg(rs: Register, typ: Type) Shift {
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return Shift{
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.Register = .{
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.register = .{
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.rs = rs.id(),
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.typ = @enumToInt(typ),
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},
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@ -400,7 +400,7 @@ pub const Instruction = union(enum) {
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pub fn imm(amount: u5, typ: Type) Shift {
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return Shift{
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.Immediate = .{
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.immediate = .{
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.amount = amount,
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.typ = @enumToInt(typ),
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},
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@ -410,14 +410,14 @@ pub const Instruction = union(enum) {
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pub fn toU12(self: Operand) u12 {
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return switch (self) {
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.Register => |v| @bitCast(u12, v),
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.Immediate => |v| @bitCast(u12, v),
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.register => |v| @bitCast(u12, v),
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.immediate => |v| @bitCast(u12, v),
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};
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}
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pub fn reg(rm: Register, shift: Shift) Operand {
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return Operand{
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.Register = .{
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.register = .{
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.rm = rm.id(),
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.shift = shift.toU8(),
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},
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@ -426,7 +426,7 @@ pub const Instruction = union(enum) {
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pub fn imm(immediate: u8, rotate: u4) Operand {
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return Operand{
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.Immediate = .{
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.immediate = .{
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.imm = immediate,
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.rotate = rotate,
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},
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@ -447,7 +447,7 @@ pub const Instruction = union(enum) {
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return for (masks) |mask, i| {
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if (x & mask == x) {
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break Operand{
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.Immediate = .{
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.immediate = .{
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.imm = @intCast(u8, std.math.rotl(u32, x, 2 * i)),
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.rotate = @intCast(u4, i),
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},
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@ -461,35 +461,67 @@ pub const Instruction = union(enum) {
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/// instruction. Data can be loaded from memory with either an
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/// immediate offset or an offset that is stored in some register.
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pub const Offset = union(enum) {
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Immediate: u12,
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Register: packed struct {
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immediate: u12,
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register: packed struct {
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rm: u4,
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shift: u8,
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fixed: u1 = 0b0,
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stype: u2,
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imm5: u5,
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},
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pub const Shift = union(enum) {
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/// No shift
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none,
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/// Logical shift left
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lsl: u5,
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/// Logical shift right
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lsr: u5,
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/// Arithmetic shift right
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asr: u5,
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/// Rotate right
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ror: u5,
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/// Rotate right one bit, with extend
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rrx,
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};
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pub const none = Offset{
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.Immediate = 0,
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.immediate = 0,
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};
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pub fn toU12(self: Offset) u12 {
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return switch (self) {
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.Register => |v| @bitCast(u12, v),
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.Immediate => |v| v,
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.register => |v| @bitCast(u12, v),
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.immediate => |v| v,
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};
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}
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pub fn reg(rm: Register, shift: u8) Offset {
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pub fn reg(rm: Register, shift: Shift) Offset {
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return Offset{
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.Register = .{
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.register = .{
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.rm = rm.id(),
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.shift = shift,
|
||||
.stype = switch (shift) {
|
||||
.none => 0b00,
|
||||
.lsl => 0b00,
|
||||
.lsr => 0b01,
|
||||
.asr => 0b10,
|
||||
.ror => 0b11,
|
||||
.rrx => 0b11,
|
||||
},
|
||||
.imm5 = switch (shift) {
|
||||
.none => 0,
|
||||
.lsl => |n| n,
|
||||
.lsr => |n| n,
|
||||
.asr => |n| n,
|
||||
.ror => |n| n,
|
||||
.rrx => 0,
|
||||
},
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn imm(immediate: u12) Offset {
|
||||
return Offset{
|
||||
.Immediate = immediate,
|
||||
.immediate = immediate,
|
||||
};
|
||||
}
|
||||
};
|
||||
@ -567,7 +599,7 @@ pub const Instruction = union(enum) {
|
||||
return Instruction{
|
||||
.data_processing = .{
|
||||
.cond = @enumToInt(cond),
|
||||
.i = @boolToInt(op2 == .Immediate),
|
||||
.i = @boolToInt(op2 == .immediate),
|
||||
.opcode = @enumToInt(opcode),
|
||||
.s = s,
|
||||
.rn = rn.id(),
|
||||
@ -681,7 +713,7 @@ pub const Instruction = union(enum) {
|
||||
.byte_word = byte_word,
|
||||
.up_down = @boolToInt(positive),
|
||||
.pre_post = @boolToInt(pre_index),
|
||||
.imm = @boolToInt(offset != .Immediate),
|
||||
.imm = @boolToInt(offset != .immediate),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user