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stage2: fix register size selection

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This actually needs proper rework, and I'll get to that when refactoring
MIR.
This commit is contained in:
Jakub Konka 2021-12-15 17:18:38 +01:00
parent 510357355a
commit 0478446377
1 changed files with 4 additions and 5 deletions
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9
src/arch/x86_64/CodeGen.zig
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@ -1635,7 +1635,7 @@ fn genBinMathOpMir(
.tag = mir_tag,
.ops = (Mir.Ops{
.reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
.reg2 = .ebp,
.reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
.flags = 0b01,
}).encode(),
.data = .{ .imm = -@intCast(i32, adj_off) },
@ -1666,7 +1666,7 @@ fn genBinMathOpMir(
.tag = mir_tag,
.ops = (Mir.Ops{
.reg1 = registerAlias(src_reg, @intCast(u32, abi_size)),
.reg2 = .ebp,
.reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
.flags = 0b10,
}).encode(),
.data = .{ .imm = -@intCast(i32, adj_off) },
@ -2835,12 +2835,11 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
}
const abi_size = ty.abiSize(self.target.*);
const adj_off = stack_offset + abi_size;
// TODO select instruction size
_ = try self.addInst(.{
.tag = .mov,
.ops = (Mir.Ops{
.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
.reg2 = .rbp,
.reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
.flags = 0b10,
}).encode(),
.data = .{ .imm = -@intCast(i32, adj_off) },
@ -3061,7 +3060,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
.tag = .mov,
.ops = (Mir.Ops{
.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
.reg2 = .ebp,
.reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
.flags = 0b01,
}).encode(),
.data = .{ .imm = ioff },