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riscv: @atomicRmw
Now we generate debug undefined constants when the user asks for them to dedup across the function decl. This takes 2 instructions instead of 7 in the RISC-V backend. TODO, we need to dedupe across function decl boundaries.
This commit is contained in:
David Rubin
parent
ea084e9519
commit
0460572899
@ -117,8 +117,9 @@ const MCValue = union(enum) {
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/// No more references to this value remain.
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/// The payload is the value of scope_generation at the point where the death occurred
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dead: u32,
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/// The value is undefined.
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undef,
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/// The value is undefined. Contains a symbol index to an undefined constant. Null means
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/// set the undefined value via immediate instead of a load.
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undef: ?u32,
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/// A pointer-sized integer that fits in a register.
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/// If the type is a pointer, this is the pointer address in virtual address space.
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immediate: u64,
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@ -1045,6 +1046,7 @@ pub fn addExtraAssumeCapacity(func: *Func, extra: anytype) u32 {
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const required_features = [_]Target.riscv.Feature{
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.d,
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.m,
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.a,
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};
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fn gen(func: *Func) !void {
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@ -1631,7 +1633,7 @@ fn computeFrameLayout(func: *Func) !FrameLayout {
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// The total frame size is calculated by the amount of s registers you need to save * 8, as each
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// register is 8 bytes, the total allocation sizes, and 16 more register for the spilled ra and s0
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// register. Finally we align the frame size to the align of the base pointer.
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// register. Finally we align the frame size to the alignment of the base pointer.
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const args_frame_size = frame_size[@intFromEnum(FrameIndex.args_frame)];
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const spill_frame_size = frame_size[@intFromEnum(FrameIndex.spill_frame)];
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const call_frame_size = frame_size[@intFromEnum(FrameIndex.call_frame)];
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@ -2110,7 +2112,7 @@ fn airNot(func: *Func, inst: Air.Inst.Index) !void {
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});
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},
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.Int => {
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const size = ty.bitSize(zcu);
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const size = ty.bitSize(pt);
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if (!math.isPowerOfTwo(size))
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return func.fail("TODO: airNot non-pow 2 int size", .{});
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@ -3249,7 +3251,7 @@ fn airWrapErrUnionErr(func: *Func, inst: Air.Inst.Index) !void {
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const frame_index = try func.allocFrameIndex(FrameAlloc.initSpill(eu_ty, pt));
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const pl_off: i32 = @intCast(errUnionPayloadOffset(pl_ty, pt));
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const err_off: i32 = @intCast(errUnionErrorOffset(pl_ty, pt));
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try func.genSetMem(.{ .frame = frame_index }, pl_off, pl_ty, .undef);
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try func.genSetMem(.{ .frame = frame_index }, pl_off, pl_ty, .{ .undef = null });
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const operand = try func.resolveInst(ty_op.operand);
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try func.genSetMem(.{ .frame = frame_index }, err_off, err_ty, operand);
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break :result .{ .load_frame = .{ .index = frame_index } };
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@ -5627,10 +5629,14 @@ fn genSetReg(func: *Func, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
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.none,
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.dead,
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=> unreachable,
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.undef => {
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.undef => |sym_index| {
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if (!func.wantSafety())
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return;
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if (sym_index) |index| {
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return func.genSetReg(ty, reg, .{ .load_symbol = .{ .sym = index } });
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}
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switch (abi_size) {
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1 => return func.genSetReg(ty, reg, .{ .immediate = 0xAA }),
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2 => return func.genSetReg(ty, reg, .{ .immediate = 0xAAAA }),
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@ -5865,11 +5871,17 @@ fn genSetMem(
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.dead,
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.reserved_frame,
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=> unreachable,
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.undef => try func.genInlineMemset(
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dst_ptr_mcv,
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src_mcv,
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.{ .immediate = abi_size },
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),
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.undef => |sym_index| {
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if (sym_index) |index| {
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return func.genSetMem(base, disp, ty, .{ .load_symbol = .{ .sym = index } });
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}
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try func.genInlineMemset(
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dst_ptr_mcv,
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src_mcv,
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.{ .immediate = abi_size },
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);
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},
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.register_offset,
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.memory,
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.indirect,
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@ -6069,12 +6081,82 @@ fn airCmpxchg(func: *Func, inst: Air.Inst.Index) !void {
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}
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fn airAtomicRmw(func: *Func, inst: Air.Inst.Index) !void {
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_ = inst;
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return func.fail("TODO implement airCmpxchg for {}", .{func.target.cpu.arch});
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const zcu = func.pt.zcu;
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const pl_op = func.air.instructions.items(.data)[@intFromEnum(inst)].pl_op;
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const extra = func.air.extraData(Air.AtomicRmw, pl_op.payload).data;
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const op = extra.op();
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const order = extra.ordering();
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const ptr_ty = func.typeOf(pl_op.operand);
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const ptr_mcv = try func.resolveInst(pl_op.operand);
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const val_ty = func.typeOf(extra.operand);
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const val_size = val_ty.abiSize(func.pt);
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const val_mcv = try func.resolveInst(extra.operand);
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if (!math.isPowerOfTwo(val_size))
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return func.fail("TODO: airAtomicRmw non-pow 2", .{});
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switch (val_ty.zigTypeTag(zcu)) {
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.Int => {},
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inline .Bool, .Float, .Enum, .Pointer => |ty| return func.fail("TODO: airAtomicRmw {s}", .{@tagName(ty)}),
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else => unreachable,
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}
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switch (val_size) {
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1, 2 => return func.fail("TODO: airAtomicRmw Int {}", .{val_size}),
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4, 8 => {},
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else => unreachable,
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}
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const ptr_register, const ptr_lock = try func.promoteReg(ptr_ty, ptr_mcv);
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defer if (ptr_lock) |lock| func.register_manager.unlockReg(lock);
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const val_register, const val_lock = try func.promoteReg(val_ty, val_mcv);
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defer if (val_lock) |lock| func.register_manager.unlockReg(lock);
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const result_mcv = try func.allocRegOrMem(val_ty, inst, true);
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assert(result_mcv == .register); // should fit into 8 bytes
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const aq, const rl = switch (order) {
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.unordered => unreachable,
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.monotonic => .{ false, false },
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.acquire => .{ true, false },
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.release => .{ false, true },
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.acq_rel => .{ true, true },
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.seq_cst => .{ true, true },
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};
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_ = try func.addInst(.{
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.tag = .pseudo,
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.ops = .pseudo_amo,
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.data = .{ .amo = .{
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.rd = result_mcv.register,
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.rs1 = ptr_register,
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.rs2 = val_register,
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.aq = if (aq) .aq else .none,
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.rl = if (rl) .rl else .none,
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.op = switch (op) {
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.Xchg => .SWAP,
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.Add => .ADD,
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.Sub => return func.fail("TODO: airAtomicRmw SUB", .{}),
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.And => .AND,
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.Nand => return func.fail("TODO: airAtomicRmw NAND", .{}),
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.Or => .OR,
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.Xor => .XOR,
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.Max => .MAX,
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.Min => .MIN,
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},
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.ty = val_ty,
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} },
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});
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return func.finishAir(inst, result_mcv, .{ pl_op.operand, extra.operand, .none });
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}
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fn airAtomicLoad(func: *Func, inst: Air.Inst.Index) !void {
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const zcu = func.bin_file.comp.module.?;
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const zcu = func.pt.zcu;
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const atomic_load = func.air.instructions.items(.data)[@intFromEnum(inst)].atomic_load;
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const order: std.builtin.AtomicOrder = atomic_load.order;
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@ -6083,6 +6165,7 @@ fn airAtomicLoad(func: *Func, inst: Air.Inst.Index) !void {
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const ptr_mcv = try func.resolveInst(atomic_load.ptr);
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const result_mcv = try func.allocRegOrMem(elem_ty, inst, true);
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assert(result_mcv == .register); // should be less than 8 bytes
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if (order == .seq_cst) {
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_ = try func.addInst(.{
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@ -6535,19 +6618,40 @@ fn getResolvedInstValue(func: *Func, inst: Air.Inst.Index) *InstTracking {
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}
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fn genTypedValue(func: *Func, val: Value) InnerError!MCValue {
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const pt = func.pt;
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const zcu = pt.zcu;
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const zcu = func.pt.zcu;
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const gpa = func.gpa;
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const owner_decl_index = zcu.funcOwnerDeclIndex(func.func_index);
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const lf = func.bin_file;
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const src_loc = func.src_loc;
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if (val.isUndef(zcu)) {
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const local_sym_index = lf.lowerUnnamedConst(func.pt, val, owner_decl_index) catch |err| {
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const msg = try ErrorMsg.create(gpa, src_loc, "lowering unnamed undefined constant failed: {s}", .{@errorName(err)});
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func.err_msg = msg;
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return error.CodegenFail;
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};
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switch (lf.tag) {
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.elf => {
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const elf_file = lf.cast(link.File.Elf).?;
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const local = elf_file.symbol(local_sym_index);
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return MCValue{ .undef = local.esym_index };
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},
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else => unreachable,
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}
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}
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const result = try codegen.genTypedValue(
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func.bin_file,
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pt,
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func.src_loc,
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lf,
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func.pt,
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src_loc,
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val,
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zcu.funcOwnerDeclIndex(func.func_index),
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owner_decl_index,
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);
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const mcv: MCValue = switch (result) {
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.mcv => |mcv| switch (mcv) {
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.none => .none,
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.undef => .undef,
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.undef => unreachable,
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.load_symbol => |sym_index| .{ .load_symbol = .{ .sym = sym_index } },
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.immediate => |imm| .{ .immediate = imm },
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.memory => |addr| .{ .memory = addr },
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@ -28,7 +28,7 @@ const OpCode = enum(u7) {
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NONE = 0b00000000,
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};
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const Fmt = enum(u2) {
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const FpFmt = enum(u2) {
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/// 32-bit single-precision
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S = 0b00,
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/// 64-bit double-precision
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@ -40,6 +40,11 @@ const Fmt = enum(u2) {
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Q = 0b11,
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};
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const AmoWidth = enum(u3) {
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W = 0b010,
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D = 0b011,
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};
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const Enc = struct {
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opcode: OpCode,
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@ -49,11 +54,15 @@ const Enc = struct {
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funct3: u3,
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funct7: u7,
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},
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amo: struct {
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funct5: u5,
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width: AmoWidth,
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},
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/// funct5 + rm + fmt
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fmt: struct {
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funct5: u5,
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rm: u3,
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fmt: Fmt,
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fmt: FpFmt,
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},
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/// funct3
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f: struct {
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@ -202,6 +211,27 @@ pub const Mnemonic = enum {
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// MISC
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fence,
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// AMO
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amoswapw,
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amoaddw,
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amoandw,
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amoorw,
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amoxorw,
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amomaxw,
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amominw,
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amomaxuw,
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amominuw,
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amoswapd,
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amoaddd,
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amoandd,
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amoord,
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amoxord,
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amomaxd,
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amomind,
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amomaxud,
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amominud,
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pub fn encoding(mnem: Mnemonic) Enc {
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return switch (mnem) {
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// zig fmt: off
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@ -379,7 +409,34 @@ pub const Mnemonic = enum {
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// MISC_MEM
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.fence => .{ .opcode = .MISC_MEM, .data = .{ .f = .{ .funct3 = 0b000 } } },
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// AMO
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.amoaddw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b00000 } } },
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.amoswapw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b00001 } } },
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// LR.W
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// SC.W
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.amoxorw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b00100 } } },
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.amoandw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b01100 } } },
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.amoorw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b01000 } } },
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.amominw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b10000 } } },
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.amomaxw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b10100 } } },
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.amominuw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b11000 } } },
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.amomaxuw => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .W, .funct5 = 0b11100 } } },
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.amoaddd => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b00000 } } },
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.amoswapd => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b00001 } } },
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// LR.D
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// SC.D
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.amoxord => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b00100 } } },
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.amoandd => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b01100 } } },
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.amoord => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b01000 } } },
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.amomind => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b10000 } } },
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.amomaxd => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b10100 } } },
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.amominud => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b11000 } } },
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.amomaxud => .{ .opcode = .AMO, .data = .{ .amo = .{ .width = .D, .funct5 = 0b11100 } } },
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// zig fmt: on
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};
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@ -395,6 +452,7 @@ pub const InstEnc = enum {
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U,
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J,
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fence,
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amo,
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/// extras that have unusual op counts
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system,
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@ -526,21 +584,43 @@ pub const InstEnc = enum {
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.fence,
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=> .fence,
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.amoswapw,
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.amoaddw,
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.amoandw,
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.amoorw,
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.amoxorw,
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.amomaxw,
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.amominw,
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.amomaxuw,
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.amominuw,
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.amoswapd,
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.amoaddd,
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.amoandd,
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.amoord,
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.amoxord,
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.amomaxd,
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.amomind,
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.amomaxud,
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.amominud,
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=> .amo,
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};
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}
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pub fn opsList(enc: InstEnc) [4]std.meta.FieldEnum(Operand) {
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pub fn opsList(enc: InstEnc) [5]std.meta.FieldEnum(Operand) {
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return switch (enc) {
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// zig fmt: off
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.R => .{ .reg, .reg, .reg, .none },
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.R4 => .{ .reg, .reg, .reg, .reg },
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.I => .{ .reg, .reg, .imm, .none },
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.S => .{ .reg, .reg, .imm, .none },
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.B => .{ .reg, .reg, .imm, .none },
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.U => .{ .reg, .imm, .none, .none },
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.J => .{ .reg, .imm, .none, .none },
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.system => .{ .none, .none, .none, .none },
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.fence => .{ .barrier, .barrier, .none, .none },
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.R => .{ .reg, .reg, .reg, .none, .none, },
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.R4 => .{ .reg, .reg, .reg, .reg, .none, },
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.I => .{ .reg, .reg, .imm, .none, .none, },
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.S => .{ .reg, .reg, .imm, .none, .none, },
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.B => .{ .reg, .reg, .imm, .none, .none, },
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.U => .{ .reg, .imm, .none, .none, .none, },
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.J => .{ .reg, .imm, .none, .none, .none, },
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.system => .{ .none, .none, .none, .none, .none, },
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.fence => .{ .barrier, .barrier, .none, .none, .none, },
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.amo => .{ .reg, .reg, .reg, .barrier, .barrier },
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// zig fmt: on
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};
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}
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@ -611,19 +691,29 @@ pub const Data = union(InstEnc) {
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pred: u4,
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_ignored: u4 = 0,
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},
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system: void,
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amo: packed struct {
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opcode: u7,
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rd: u5,
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funct3: u3,
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rs1: u5,
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rs2: u5,
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rl: bool,
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aq: bool,
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funct5: u5,
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},
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system: u32,
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comptime {
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for (std.meta.fields(Data)) |field| {
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||||
assert(@bitSizeOf(field.type) == 32);
|
||||
}
|
||||
}
|
||||
|
||||
pub fn toU32(self: Data) u32 {
|
||||
return switch (self) {
|
||||
// zig fmt: off
|
||||
.R => |v| @bitCast(v),
|
||||
.R4 => |v| @bitCast(v),
|
||||
.I => |v| @bitCast(v),
|
||||
.S => |v| @bitCast(v),
|
||||
.B => |v| @as(u32, @intCast(v.opcode)) + (@as(u32, @intCast(v.imm11)) << 7) + (@as(u32, @intCast(v.imm1_4)) << 8) + (@as(u32, @intCast(v.funct3)) << 12) + (@as(u32, @intCast(v.rs1)) << 15) + (@as(u32, @intCast(v.rs2)) << 20) + (@as(u32, @intCast(v.imm5_10)) << 25) + (@as(u32, @intCast(v.imm12)) << 31),
|
||||
.U => |v| @bitCast(v),
|
||||
.J => |v| @bitCast(v),
|
||||
.fence => |v| @bitCast(v),
|
||||
inline else => |v| @bitCast(v),
|
||||
.system => unreachable,
|
||||
// zig fmt: on
|
||||
};
|
||||
@ -792,6 +882,34 @@ pub const Data = union(InstEnc) {
|
||||
},
|
||||
};
|
||||
},
|
||||
.amo => {
|
||||
assert(ops.len == 5);
|
||||
|
||||
const rd = ops[0];
|
||||
const rs1 = ops[1];
|
||||
const rs2 = ops[2];
|
||||
const rl = ops[3];
|
||||
const aq = ops[4];
|
||||
|
||||
const ret: Data = .{
|
||||
.amo = .{
|
||||
.rd = rd.reg.encodeId(),
|
||||
.rs1 = rs1.reg.encodeId(),
|
||||
.rs2 = rs2.reg.encodeId(),
|
||||
|
||||
// TODO: https://github.com/ziglang/zig/issues/20113
|
||||
.rl = if (rl.barrier == .rl) true else false,
|
||||
.aq = if (aq.barrier == .aq) true else false,
|
||||
|
||||
.opcode = @intFromEnum(enc.opcode),
|
||||
.funct3 = @intFromEnum(enc.data.amo.width),
|
||||
.funct5 = enc.data.amo.funct5,
|
||||
},
|
||||
};
|
||||
|
||||
std.debug.print("ret: {}, {}", .{ ret.amo.rl, rl.barrier == .rl });
|
||||
return ret;
|
||||
},
|
||||
|
||||
else => std.debug.panic("TODO: construct {s}", .{@tagName(inst_enc)}),
|
||||
}
|
||||
|
||||
@ -412,6 +412,32 @@ pub fn lowerMir(lower: *Lower, index: Mir.Inst.Index) Error!struct {
|
||||
});
|
||||
},
|
||||
|
||||
.pseudo_amo => {
|
||||
const amo = inst.data.amo;
|
||||
const is_d = amo.ty.abiSize(pt) == 8;
|
||||
const is_un = amo.ty.isUnsignedInt(pt.zcu);
|
||||
|
||||
const mnem: Encoding.Mnemonic = switch (amo.op) {
|
||||
// zig fmt: off
|
||||
.SWAP => if (is_d) .amoswapd else .amoswapw,
|
||||
.ADD => if (is_d) .amoaddd else .amoaddw,
|
||||
.AND => if (is_d) .amoandd else .amoandw,
|
||||
.OR => if (is_d) .amoord else .amoorw,
|
||||
.XOR => if (is_d) .amoxord else .amoxorw,
|
||||
.MAX => if (is_d) if (is_un) .amomaxud else .amomaxd else if (is_un) .amomaxuw else .amomaxw,
|
||||
.MIN => if (is_d) if (is_un) .amominud else .amomind else if (is_un) .amominuw else .amominw,
|
||||
// zig fmt: on
|
||||
};
|
||||
|
||||
try lower.emit(mnem, &.{
|
||||
.{ .reg = inst.data.amo.rd },
|
||||
.{ .reg = inst.data.amo.rs1 },
|
||||
.{ .reg = inst.data.amo.rs2 },
|
||||
.{ .barrier = inst.data.amo.rl },
|
||||
.{ .barrier = inst.data.amo.aq },
|
||||
});
|
||||
},
|
||||
|
||||
else => return lower.fail("TODO lower: psuedo {s}", .{@tagName(inst.ops)}),
|
||||
},
|
||||
}
|
||||
|
||||
@ -39,8 +39,6 @@ pub const Inst = struct {
|
||||
ecall,
|
||||
unimp,
|
||||
|
||||
fence,
|
||||
|
||||
add,
|
||||
addw,
|
||||
sub,
|
||||
@ -82,6 +80,8 @@ pub const Inst = struct {
|
||||
sh,
|
||||
sb,
|
||||
|
||||
fence,
|
||||
|
||||
// M extension
|
||||
mul,
|
||||
mulw,
|
||||
@ -136,6 +136,9 @@ pub const Inst = struct {
|
||||
fltd,
|
||||
fled,
|
||||
|
||||
/// A Extension Instructions
|
||||
amo,
|
||||
|
||||
/// A pseudo-instruction. Used for anything that isn't 1:1 with an
|
||||
/// assembly instruction.
|
||||
pseudo,
|
||||
@ -254,6 +257,16 @@ pub const Inst = struct {
|
||||
pred: Barrier,
|
||||
succ: Barrier,
|
||||
},
|
||||
|
||||
amo: struct {
|
||||
rd: Register,
|
||||
rs1: Register,
|
||||
rs2: Register,
|
||||
aq: Barrier,
|
||||
rl: Barrier,
|
||||
op: AmoOp,
|
||||
ty: Type,
|
||||
},
|
||||
};
|
||||
|
||||
pub const Ops = enum {
|
||||
@ -343,6 +356,9 @@ pub const Inst = struct {
|
||||
|
||||
/// IORW, IORW
|
||||
fence,
|
||||
|
||||
/// Ordering, Src, Addr, Dest
|
||||
pseudo_amo,
|
||||
};
|
||||
|
||||
// Make sure we don't accidentally make instructions bigger than expected.
|
||||
@ -379,9 +395,25 @@ pub const FrameLoc = struct {
|
||||
};
|
||||
|
||||
pub const Barrier = enum(u4) {
|
||||
// Fence
|
||||
r = 0b0001,
|
||||
w = 0b0010,
|
||||
rw = 0b0011,
|
||||
|
||||
// Amo
|
||||
none,
|
||||
aq,
|
||||
rl,
|
||||
};
|
||||
|
||||
pub const AmoOp = enum(u5) {
|
||||
SWAP,
|
||||
ADD,
|
||||
AND,
|
||||
OR,
|
||||
XOR,
|
||||
MAX,
|
||||
MIN,
|
||||
};
|
||||
|
||||
/// Returns the requested data, as well as the new index which is at the start of the
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
pub const Instruction = struct {
|
||||
encoding: Encoding,
|
||||
ops: [4]Operand = .{.none} ** 4,
|
||||
ops: [5]Operand = .{.none} ** 5,
|
||||
|
||||
pub const Operand = union(enum) {
|
||||
none,
|
||||
@ -12,16 +12,18 @@ pub const Instruction = struct {
|
||||
|
||||
pub fn new(mnemonic: Encoding.Mnemonic, ops: []const Operand) !Instruction {
|
||||
const encoding = (try Encoding.findByMnemonic(mnemonic, ops)) orelse {
|
||||
std.log.err("no encoding found for: {s} [{s} {s} {s}]", .{
|
||||
std.log.err("no encoding found for: {s} [{s} {s} {s} {s} {s}]", .{
|
||||
@tagName(mnemonic),
|
||||
@tagName(if (ops.len > 0) ops[0] else .none),
|
||||
@tagName(if (ops.len > 1) ops[1] else .none),
|
||||
@tagName(if (ops.len > 2) ops[2] else .none),
|
||||
@tagName(if (ops.len > 3) ops[3] else .none),
|
||||
@tagName(if (ops.len > 4) ops[4] else .none),
|
||||
});
|
||||
return error.InvalidInstruction;
|
||||
};
|
||||
|
||||
var result_ops: [4]Operand = .{.none} ** 4;
|
||||
var result_ops: [5]Operand = .{.none} ** 5;
|
||||
@memcpy(result_ops[0..ops.len], ops);
|
||||
|
||||
return .{
|
||||
|
||||
@ -987,8 +987,9 @@ pub fn genTypedValue(
|
||||
|
||||
log.debug("genTypedValue: val = {}", .{val.fmtValue(pt, null)});
|
||||
|
||||
if (val.isUndef(zcu))
|
||||
if (val.isUndef(zcu)) {
|
||||
return GenResult.mcv(.undef);
|
||||
}
|
||||
|
||||
const owner_decl = zcu.declPtr(owner_decl_index);
|
||||
const namespace = zcu.namespacePtr(owner_decl.src_namespace);
|
||||
|
||||
@ -540,8 +540,8 @@ inline fn isGlobal(index: Symbol.Index) bool {
|
||||
|
||||
pub fn symbol(self: ZigObject, index: Symbol.Index) Symbol.Index {
|
||||
const actual_index = index & symbol_mask;
|
||||
if (isGlobal(index)) return self.global_symbols.items[actual_index];
|
||||
return self.local_symbols.items[actual_index];
|
||||
if (isGlobal(index)) return self.globals()[actual_index];
|
||||
return self.locals()[actual_index];
|
||||
}
|
||||
|
||||
pub fn elfSym(self: *ZigObject, index: Symbol.Index) *elf.Elf64_Sym {
|
||||
@ -1334,11 +1334,15 @@ fn lowerConst(
|
||||
|
||||
const sym_index = try self.addAtom(elf_file);
|
||||
|
||||
const res = try codegen.generateSymbol(&elf_file.base, pt, src_loc, val, &code_buffer, .{
|
||||
.none = {},
|
||||
}, .{
|
||||
.parent_atom_index = sym_index,
|
||||
});
|
||||
const res = try codegen.generateSymbol(
|
||||
&elf_file.base,
|
||||
pt,
|
||||
src_loc,
|
||||
val,
|
||||
&code_buffer,
|
||||
.{ .none = {} },
|
||||
.{ .parent_atom_index = sym_index },
|
||||
);
|
||||
const code = switch (res) {
|
||||
.ok => code_buffer.items,
|
||||
.fail => |em| return .{ .fail = em },
|
||||
|
||||
@ -188,21 +188,6 @@ test "atomic store" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
|
||||
|
||||
var x: u32 = 0;
|
||||
@atomicStore(u32, &x, 1, .seq_cst);
|
||||
try expect(@atomicLoad(u32, &x, .seq_cst) == 1);
|
||||
@atomicStore(u32, &x, 12345678, .seq_cst);
|
||||
try expect(@atomicLoad(u32, &x, .seq_cst) == 12345678);
|
||||
}
|
||||
|
||||
test "atomic store comptime" {
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
|
||||
|
||||
try comptime testAtomicStore();
|
||||
try testAtomicStore();
|
||||
@ -451,7 +436,6 @@ test "return @atomicStore, using it as a void value" {
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
|
||||
|
||||
const S = struct {
|
||||
const A = struct {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user