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Riscv32e align stack to 4 bytes (#20673)

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cheme 2024-07-21 07:28:22 +00:00 committed by GitHub
parent 397be0c9cc
commit 01dc0d5a72
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2 changed files with 4 additions and 2 deletions
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3
lib/std/Target.zig
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@ -1967,7 +1967,6 @@ pub fn stackAlignment(target: Target) u16 {
.bpfel,
.mips64,
.mips64el,
.riscv32,
.riscv64,
.sparc64,
.x86_64,
@ -1976,6 +1975,8 @@ pub fn stackAlignment(target: Target) u16 {
.wasm64,
.loongarch64,
=> 16,
.riscv32,
=> if (Target.riscv.featureSetHas(target.cpu.features, .e)) 4 else 16,
.powerpc64,
.powerpc64le,
=> switch (target.os.tag) {

3
src/codegen/llvm.zig
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@ -542,7 +542,8 @@ const DataLayoutBuilder = struct {
try self.typeAlignment(.float, 64, 64, 64, true, writer);
}
if (stack_abi != ptr_bit_width or self.target.cpu.arch == .msp430 or
self.target.os.tag == .uefi or self.target.os.tag == .windows)
self.target.os.tag == .uefi or self.target.os.tag == .windows or
self.target.cpu.arch == .riscv32)
try writer.print("-S{d}", .{stack_abi});
switch (self.target.cpu.arch) {
.hexagon, .ve => {