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x64: refactor fix reg aliasing in genSetReg

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This commit is contained in:
Jakub Konka 2022-03-21 23:38:01 +01:00
parent 79e2d4b3f6
commit 00e2113c8b
2 changed files with 7 additions and 7 deletions
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13
src/arch/x86_64/CodeGen.zig
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@ -953,8 +953,7 @@ pub fn spillCompareFlagsIfOccupied(self: *Self) !void {
/// This can have a side effect of spilling instructions to the stack to free up a register. /// This can have a side effect of spilling instructions to the stack to free up a register.
fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register { fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
const reg = try self.register_manager.allocReg(null); const reg = try self.register_manager.allocReg(null);
const sized_reg = registerAlias(reg, @intCast(u32, ty.abiSize(self.target.*))); try self.genSetReg(ty, reg, mcv);
try self.genSetReg(ty, sized_reg, mcv);
return reg; return reg;
} }
@ -5201,7 +5200,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
if (!self.wantSafety()) if (!self.wantSafety())
return; // The already existing value will do just fine. return; // The already existing value will do just fine.
// Write the debug undefined value. // Write the debug undefined value.
switch (reg.size()) { switch (registerAlias(reg, abi_size).size()) {
8 => return self.genSetReg(ty, reg, .{ .immediate = 0xaa }), 8 => return self.genSetReg(ty, reg, .{ .immediate = 0xaa }),
16 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaa }), 16 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaa }),
32 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaaaaaa }), 32 => return self.genSetReg(ty, reg, .{ .immediate = 0xaaaaaaaa }),
@ -5338,7 +5337,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
_ = try self.addInst(.{ _ = try self.addInst(.{
.tag = .mov, .tag = .mov,
.ops = (Mir.Ops{ .ops = (Mir.Ops{
.reg1 = reg, .reg1 = registerAlias(reg, abi_size),
.reg2 = reg.to64(), .reg2 = reg.to64(),
.flags = 0b01, .flags = 0b01,
}).encode(), }).encode(),
@ -5351,7 +5350,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
_ = try self.addInst(.{ _ = try self.addInst(.{
.tag = .mov, .tag = .mov,
.ops = (Mir.Ops{ .ops = (Mir.Ops{
.reg1 = reg, .reg1 = registerAlias(reg, abi_size),
.flags = 0b01, .flags = 0b01,
}).encode(), }).encode(),
.data = .{ .imm = @truncate(u32, x) }, .data = .{ .imm = @truncate(u32, x) },
@ -5378,8 +5377,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
_ = try self.addInst(.{ _ = try self.addInst(.{
.tag = .mov, .tag = .mov,
.ops = (Mir.Ops{ .ops = (Mir.Ops{
.reg1 = reg, .reg1 = registerAlias(reg, abi_size),
.reg2 = reg, .reg2 = reg.to64(),
.flags = 0b01, .flags = 0b01,
}).encode(), }).encode(),
.data = .{ .imm = 0 }, .data = .{ .imm = 0 },

1
test/behavior/eval.zig
View File

@ -424,6 +424,7 @@ test "f64 at compile time is lossy" {
} }
test { test {
if (builtin.zig_backend != .stage1 and builtin.os.tag == .macos) return error.SkipZigTest;
comptime try expect(@as(f128, 1 << 113) == 10384593717069655257060992658440192); comptime try expect(@as(f128, 1 << 113) == 10384593717069655257060992658440192);
} }